Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31753 )
Change subject: device/pci_ops: Have only default PCI bus ops available ......................................................................
device/pci_ops: Have only default PCI bus ops available
In the current state of the tree we do not utilise the mechanism of having per-device overrides for PCI bus ops.
This change effectively inlines all PCI config accessors for ramstage as well.
Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/arch/x86/Makefile.inc M src/arch/x86/include/arch/pci_ops.h D src/arch/x86/pci_ops.c D src/arch/x86/pci_ops_conf1.c M src/device/Makefile.inc D src/device/pci_ops_mmconf.c M src/include/device/device.h M src/include/device/pci.h M src/include/device/pci_ops.h 9 files changed, 7 insertions(+), 133 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Aaron Durbin: Looks good to me, approved
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index e3151ef..6e4ee76 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -327,8 +327,6 @@ ramstage-y += memset.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c -ramstage-y += pci_ops_conf1.c -ramstage-$(CONFIG_NO_MMCONF_SUPPORT) += pci_ops.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 67633f4..e706216 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -17,10 +17,4 @@ #include <arch/pci_io_cfg.h> #include <device/pci_mmio_cfg.h>
-#ifndef __SIMPLE_DEVICE__ - -extern const struct pci_bus_operations pci_cf8_conf1; - -#endif - #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/arch/x86/pci_ops.c b/src/arch/x86/pci_ops.c deleted file mode 100644 index f30bffe..0000000 --- a/src/arch/x86/pci_ops.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci_ops.h> - -const struct pci_bus_operations *pci_bus_default_ops(void) -{ - return &pci_cf8_conf1; -} diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c deleted file mode 100644 index 03c2b64..0000000 --- a/src/arch/x86/pci_ops_conf1.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <arch/pci_io_cfg.h> - -/* - * Functions for accessing PCI configuration space with type 1 accesses - */ - -const struct pci_bus_operations pci_cf8_conf1 = { - .read8 = pci_io_read_config8, - .read16 = pci_io_read_config16, - .read32 = pci_io_read_config32, - .write8 = pci_io_write_config8, - .write16 = pci_io_write_config16, - .write32 = pci_io_write_config32, -}; diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index c325a7e..711a403 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -33,7 +33,6 @@ ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c -ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c endif
subdirs-y += oprom dram diff --git a/src/device/pci_ops_mmconf.c b/src/device/pci_ops_mmconf.c deleted file mode 100644 index 2fcb961..0000000 --- a/src/device/pci_ops_mmconf.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_mmio_cfg.h> - -#if (CONFIG_MMCONF_BASE_ADDRESS == 0) -#error "CONFIG_MMCONF_BASE_ADDRESS needs to be non-zero!" -#endif - -/* - * Functions for accessing PCI configuration space with mmconf accesses - */ - -static const struct pci_bus_operations pci_ops_mmconf = { - .read8 = pci_mmio_read_config8, - .read16 = pci_mmio_read_config16, - .read32 = pci_mmio_read_config32, - .write8 = pci_mmio_write_config8, - .write16 = pci_mmio_write_config16, - .write32 = pci_mmio_write_config32, -}; - -const struct pci_bus_operations *pci_bus_default_ops(void) -{ - return &pci_ops_mmconf; -} diff --git a/src/include/device/device.h b/src/include/device/device.h index 2e2cda9..7d7be73 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -17,7 +17,6 @@
struct device; struct pci_operations; -struct pci_bus_operations; struct i2c_bus_operations; struct smbus_bus_operations; struct pnp_mode_ops; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 14c4693..f1de7bf 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> +#include <device/pci_ops.h> #include <device/pci_rom.h> #include <device/pci_type.h>
@@ -33,19 +34,6 @@ void (*set_L1_ss_latency)(struct device *dev, unsigned int off); };
-/* Common pci bus operations */ -struct pci_bus_operations { - uint8_t (*read8)(pci_devfn_t dev, uint16_t reg); - uint16_t (*read16)(pci_devfn_t dev, uint16_t reg); - uint32_t (*read32)(pci_devfn_t dev, uint16_t reg); - void (*write8)(pci_devfn_t dev, uint16_t reg, uint8_t val); - void (*write16)(pci_devfn_t dev, uint16_t reg, uint16_t val); - void (*write32)(pci_devfn_t dev, uint16_t reg, uint32_t val); -}; - -// FIXME: Needs complete pci_bus_operations -#include <device/pci_ops.h> - struct pci_driver { const struct device_operations *ops; unsigned short vendor; diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index bb77754..454795f 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -39,13 +39,6 @@
#include <device/pci.h>
-const struct pci_bus_operations *pci_bus_default_ops(void); - -static __always_inline const struct pci_bus_operations *pci_bus_ops(void) -{ - return pci_bus_default_ops(); -} - void __noreturn pcidev_die(void);
static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) @@ -63,43 +56,37 @@ static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg) { - pci_devfn_t bdf = PCI_BDF(dev); - return pci_bus_ops()->read8(bdf, reg); + return pci_s_read_config8(PCI_BDF(dev), reg); }
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg) { - pci_devfn_t bdf = PCI_BDF(dev); - return pci_bus_ops()->read16(bdf, reg); + return pci_s_read_config16(PCI_BDF(dev), reg); }
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg) { - pci_devfn_t bdf = PCI_BDF(dev); - return pci_bus_ops()->read32(bdf, reg); + return pci_s_read_config32(PCI_BDF(dev), reg); }
static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val) { - pci_devfn_t bdf = PCI_BDF(dev); - pci_bus_ops()->write8(bdf, reg, val); + pci_s_write_config8(PCI_BDF(dev), reg, val); }
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val) { - pci_devfn_t bdf = PCI_BDF(dev); - pci_bus_ops()->write16(bdf, reg, val); + pci_s_write_config16(PCI_BDF(dev), reg, val); }
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val) { - pci_devfn_t bdf = PCI_BDF(dev); - pci_bus_ops()->write32(bdf, reg, val); + pci_s_write_config32(PCI_BDF(dev), reg, val); }
#endif