[coreboot-gerrit] Change in coreboot[master]: soc/intel/adl: Update devicetree based on remapping for TBT PCIe

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61295 )

Change subject: soc/intel/adl: Update devicetree based on remapping for TBT PCIe
......................................................................

soc/intel/adl: Update devicetree based on remapping for TBT PCIe

ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe
coalescing logic where in case root port 0 is disabled, other enabled
root port is remapped to port 0.

coreboot handles this remapping scenarios for PCH and CPU PCIe root
ports and not for TBT root ports.

This patch uses the same function used for PCIe remapping to update
devicetree based on coalescing and SoC needs to pass correct function
number and number of slots.

BUG=b:210933428
BRANCH=None
TEST=Check if TBT remapping happens correctly and ACPI tables are
generated correctly.

Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010
Signed-off-by: MAULIK V VAGHELA 
Signed-off-by: Meera Ravindranath 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: EricR Lai 
Reviewed-by: Nico Huber 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.c
M src/soc/intel/alderlake/include/soc/pcie.h
M src/soc/intel/alderlake/pcie_rp.c
4 files changed, 20 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve
  EricR Lai: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 89d0c93..dc7d32b 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -207,6 +207,12 @@
    default 0 if SOC_INTEL_ALDERLAKE_PCH_N
    default 3 if SOC_INTEL_ALDERLAKE_PCH_P

+config MAX_TBT_ROOT_PORTS
+	int
+	default 0 if SOC_INTEL_ALDERLAKE_PCH_N
+	default 2 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 4 if SOC_INTEL_ALDERLAKE_PCH_P
+
 config MAX_ROOT_PORTS
    int
    default MAX_PCH_ROOT_PORTS
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 1fa78fb..9127c5e 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -142,6 +142,9 @@

/* Swap enabled PCI ports in device tree if needed. */
    pcie_rp_update_devicetree(get_pch_pcie_rp_table());
+
+	/* Swap enabled TBT root ports in device tree if needed. */
+	pcie_rp_update_devicetree(get_tbt_pcie_rp_table());
 }

static void cpu_fill_ssdt(const struct device *dev)
diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h
index cd76d09..6b3ca54 100644
--- a/src/soc/intel/alderlake/include/soc/pcie.h
+++ b/src/soc/intel/alderlake/include/soc/pcie.h
@@ -7,5 +7,6 @@

const struct pcie_rp_group *get_pch_pcie_rp_table(void);
 const struct pcie_rp_group *get_cpu_pcie_rp_table(void);
+const struct pcie_rp_group *get_tbt_pcie_rp_table(void);

#endif /* __SOC_ALDERLAKE_PCIE_H__ */
diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c
index 26ce785..f38105a 100644
--- a/src/soc/intel/alderlake/pcie_rp.c
+++ b/src/soc/intel/alderlake/pcie_rp.c
@@ -61,6 +61,16 @@
    return cpu_rp_groups;
 }

+static const struct pcie_rp_group tbt_rp_groups[] = {
+	{ .slot = SA_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS},
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_tbt_pcie_rp_table(void)
+{
+	return tbt_rp_groups;
+}
+
 static bool is_part_of_group(const struct device *dev,
    		     const struct pcie_rp_group *groups)
 {

6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.