[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47537 )

Change subject: soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF
......................................................................

soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF

Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes
coreboot in control of these settings.

Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/common/block/p2sb/Makefile.inc
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/include/soc/pch.h
M src/soc/intel/xeon_sp/pch.c
M src/soc/intel/xeon_sp/skx/chip.c
6 files changed, 27 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/47537/1

diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc
index a1330ab..d557e36 100644
--- a/src/soc/intel/common/block/p2sb/Makefile.inc
+++ b/src/soc/intel/common/block/p2sb/Makefile.inc
@@ -1,3 +1,4 @@
 bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
 smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index a10075a..2e50e64 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -9,7 +9,7 @@
 romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
 romstage-y += ../../../cpu/intel/car/romstage.c
 ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c
-ramstage-y += memmap.c
+ramstage-y += memmap.c pch.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 postcar-y += spi.c
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 3daff13..7ca40e3 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -11,6 +11,7 @@
 #include <soc/chip_common.h>
 #include <soc/cpu.h>
 #include <soc/ramstage.h>
+#include <soc/pch.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>

@@ -72,6 +73,7 @@
 {
    printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
    fsp_silicon_init(false);
+	override_hpet_ioapic_bdf();
    pch_enable_ioapic();
    setup_lapic();
    p2sb_unhide();
diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h
index 84d5e48..0be14ae 100644
--- a/src/soc/intel/xeon_sp/include/soc/pch.h
+++ b/src/soc/intel/xeon_sp/include/soc/pch.h
@@ -9,4 +9,6 @@
 void pch_disable_devfn(struct device *dev);
 #endif

+void override_hpet_ioapic_bdf(void);
+
 #endif /* _SOC_PCH_H_ */
diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c
index 5427952..8d28592 100644
--- a/src/soc/intel/xeon_sp/pch.c
+++ b/src/soc/intel/xeon_sp/pch.c
@@ -5,7 +5,9 @@
 #include <soc/pcr_ids.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
+#include <intelblocks/p2sb.h>
 #include <soc/bootblock.h>
+#include <soc/pch.h>
 #include <soc/pmc.h>
 #include <console/console.h>

@@ -48,3 +50,20 @@
     */
    soc_config_acpibase();
 }
+
+void override_hpet_ioapic_bdf(void)
+{
+	union p2sb_bdf ioapic_bdf = {
+		.bus = PCH_IOAPIC_BUS_NUMBER,
+		.dev = PCH_IOAPIC_DEV_NUM,
+		.fn = PCH_IOAPIC_FUNC_NUM,
+	};
+	union p2sb_bdf hpet_bdf = {
+		.bus = HPET_BUS_NUM,
+		.dev = HPET_DEV_NUM,
+		.fn = HPET0_FUNC_NUM,
+	};
+
+	p2sb_set_ioapic_bdf(ioapic_bdf);
+	p2sb_set_hpet_bdf(hpet_bdf);
+}
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index a345c3e..0b57d20 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -6,6 +6,7 @@
 #include <soc/acpi.h>
 #include <soc/chip_common.h>
 #include <soc/ramstage.h>
+#include <soc/pch.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>

@@ -43,6 +44,7 @@
 {
    printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
    fsp_silicon_init(false);
+	override_hpet_ioapic_bdf();
 }

static void soc_final(void *data)