Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.
Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75559?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
Change subject: soc/amd/phoenix/chip: use common data fabric domain resource code ......................................................................
soc/amd/phoenix/chip: use common data fabric domain resource code
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt.
BUG=b:283495475 TEST=Myst still boots and both the coreboot console and the kernel show the expected PCI MMIO ranges being used.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I425876c4ef470574e00e123d36101641240c98cf --- M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/acpi/pci0.asl M src/soc/amd/phoenix/chip.c M src/soc/amd/phoenix/root_complex.c 4 files changed, 4 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/75559/8