Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10999
-gerrit
commit 1686ca7841c1b79e7d968cbeccc5ef0418699c2b Author: Naveen Krishna Chatradhi naveenkrishna.ch@intel.com Date: Mon May 18 21:25:52 2015 +0530
intel/skylake: support 32bit uart8250_mem driver in romstage
This patch adds 32bit uart8250_mem functionality in romstage console for arch/x86.
BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp; verified romstage logs on RVP3 board.
Change-Id: I6f13216b7f5ba8de48c781cd1791d0fa7ae0d921 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: a17efdeec5524cbfc78015c358d1cf4f67485765 Original-Change-Id: I8b4e44c59bfd609a06807243df338763054b5865 Original-Signed-off-by: Naveen Krishna Chatradhi naveenkrishna.ch@intel.com Original-Signed-off-by: Rishavnath Satapathy rishavnath.satapathy@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/271800 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Commit-Queue: Wenkai Du wenkai.du@intel.com Original-Tested-by: Wenkai Du wenkai.du@intel.com --- src/soc/intel/skylake/romstage/uart.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index c53643a..afc8c63 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -57,8 +57,9 @@ void pch_uart_init(void) write32(base + SIO_REG_PPR_CLOCK, tmp);
/* Put UART2 in byte access mode for 16550 compatibility */ - pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, - SIO_PCH_LEGACY_UART2); + if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32)) + pcr_andthenor32(PID_SERIALIO, + R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2);
/* Configure GPIO for UART2 in native mode*/ uartgpioinit(FALSE);