[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/p2sb: Add helper function to enable BAR

[Subrata Banik (Code Review)]

Attention is currently required from: Wonkyu Kim, Tim Wawrzynczak, John Zhao, Angel Pons, Nick Vaccaro, Eric Lai, Patrick Rudolph, Felix Held.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62778 )

Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR
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Patch Set 3:

(1 comment)

File src/soc/intel/common/block/p2sb/p2sblib.c:

https://review.coreboot.org/c/coreboot/+/62778/comment/b8959c09_8306c8a1 
PS3, Line 13: uint32_t low_bar, uint32_t high_bar
> In this topic, just wondering would pci support 64 bit read/write 😎

I thought Felix meant like this

void p2sb_dev_enable_bar(pci_devfn_t dev, uint64_t bar)
{
    /* Enable PCR Base addresses */
    pci_write_config32(dev, PCI_BASE_ADDRESS_0, (uint32_t)bar);
    pci_write_config32(dev, PCI_BASE_ADDRESS_1, (uint32_t)(bar >> 32));
       ....
}