Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47397 )
Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support ......................................................................
soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
Add MMIO offsets for USB2 and USB3 port status registers; implement soc_get_xhci_usb_info() to return the info for elog.
Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- A src/soc/intel/alderlake/xhci.c 1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47397/1
diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c new file mode 100644 index 0000000..ab2a48c --- /dev/null +++ b/src/soc/intel/alderlake/xhci.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/xhci.h> + +/* + * Information obtained from Intel doc# 630094, ADL-P PCH EDS Vol. 2, + * as well as doc# 626817, ADL-P PCH EDS Vol. 1 + */ + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x540 +#define XHCI_USB2_PORT_NUM 10 +#define XHCI_USB3_PORT_NUM 4 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +}