[coreboot-gerrit] Change in ...coreboot[master]: mb/emulation/qemu-riscv: Use generic 8250 uart driver

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33735 )

Change subject: mb/emulation/qemu-riscv: Use generic 8250 uart driver
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Patch Set 1:

The change brings in dependency of udelay(), so printk() before mtime_init() in riscv/mcall.c:hls_init() is wrong. It's BIOS_SPEW and UART code may never actually reach the udelay(), but there's a possible die() there in the path for this case.

Looking into riscv/arch_timer.c:timer_monotonic_get(), HLS()->time seems uninitialized and probably does not reference the intended hardware register SIFIVE_TIME_BASE (yet).
Also, I see SIFIVE_CLINT_TIMEBASE_FREQ 10+E6 in QEMU, assuming 10 MHz or 1/10 us per tick.