[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table

[Subrata Banik (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email )

Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
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Patch Set 5:

(3 comments)

File src/soc/intel/common/block/acpi/Kconfig:

https://review.coreboot.org/c/coreboot/+/84103/comment/24b2272f_312d0643?usp... :
PS5, Line 87: 	  devices.
u should also mention that GPE1 Event Bit is an extension of GPE0 (present in all Intel SoC platform). Select this Kconfig for support SoCs that publishes GPE1 as part of PMC IO register.

File src/soc/intel/common/block/acpi/acpi.c:

https://review.coreboot.org/c/coreboot/+/84103/comment/58095ae5_e462c778?usp... :
PS5, Line 29: GPE1_STS
this won't work. I believe you can use Kconfig over macro. that is more clean solution.

https://review.coreboot.org/c/coreboot/+/84103/comment/99ac1291_1c2743fa?usp... :
PS5, Line 114: GPE1_STS(0) 
```
CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1) ? (pmbase + GPE1_STS(0)) : 0
```