[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add PCH series check for CML LP PCH

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31434 )

Change subject: soc/intel/cannonlake: Add PCH series check for CML LP PCH
......................................................................

soc/intel/cannonlake: Add PCH series check for CML LP PCH

TEST=Verify PM_STS1 value is is not 0xFF.

Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66
Signed-off-by: Maulik V Vaghela 
Reviewed-on: https://review.coreboot.org/c/31434
Reviewed-by: Subrata Banik 
Reviewed-by: Rizwan Qureshi 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/lpc.c
1 file changed, 13 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Rizwan Qureshi: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index c33b3c3..c06ce97 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -70,19 +70,25 @@
 uint8_t get_pch_series(void)
 {
    uint16_t lpc_did_hi_byte;
-
+	uint8_t pch_series = PCH_UNKNOWN_SERIES;
    /*
     * Fetch upper 8 bits on LPC device ID to determine PCH type
     * Adding 1 to the offset to fetch upper 8 bits
     */
    lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1);

-	if (lpc_did_hi_byte == 0x9D)
-		return PCH_LP;
-	else if (lpc_did_hi_byte == 0xA3)
-		return PCH_H;
-	else
-		return PCH_UNKNOWN_SERIES;
+	switch (lpc_did_hi_byte) {
+	case 0x9D: /* CNL-LP */
+	case 0x02: /* CML-LP */
+		pch_series = PCH_LP;
+		break;
+	case 0xA3:
+		pch_series = PCH_H;
+		break;
+	default:
+		break;
+	}
+	return pch_series;
 }

#if ENV_RAMSTAGE