[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 )

Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/69680/comment/d8e3139b_513fe848 
PS1, Line 9: This patch skips setting D0I3 bit for all HECI devices by FSP.
> > it's a backport  ?
>
> The original CL don't indicate why the change has done.

I hope you still have access to the https://b.corp.google.com/issues/200644229 (from original CL) which intended to fix the `super weird issue about CSE` aka Intel CSE EOP implementation is taking longer time (sometime ~60ms), average ~30ms bug.

Do you want to put that in the commit msg ?