Damien Zammit (damien@zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7172
-gerrit
commit 39c4711f75e16a07b45205c36e7085ad8680a9b6 Author: Damien Zammit damien@zamaudio.com Date: Thu Oct 23 13:21:45 2014 +1100
bd82x6x/sata: Fix AHCI mode setting and allow split mode
According to the Intel PCH 7 series datasheet, a flag must be set when in AHCI mode. This is now fixed. A second flag has been implemented to allow user selection of 6/0 or 2/4 split controller mode of ports on SATA when in IDE mode. This is a new configurable parameter called sata_port_split in the devicetree and takes the value 0 or 1.
Change-Id: I825c15d329b2d5960534b1f01843e0df3ace5317 Signed-off-by: Damien Zammit damien@zamaudio.com --- src/southbridge/intel/bd82x6x/chip.h | 1 + src/southbridge/intel/bd82x6x/sata.c | 8 ++++++++ 2 files changed, 9 insertions(+)
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 0f2f0e9..e8d1da9 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -65,6 +65,7 @@ struct southbridge_intel_bd82x6x_config {
/* IDE configuration */ uint8_t sata_port_map; + uint8_t sata_port_split; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx;
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index cb5699e..7ec33c0 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -89,6 +89,10 @@ static void sata_init(struct device *dev) reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32);
+ /* Set AHCI mode (SMS + SC) */ + reg16 = 0x0060; + pci_write_config16(dev, 0x90, reg16); + /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; /* 6 ports SKU + ORM */ @@ -163,6 +167,10 @@ static void sata_init(struct device *dev) reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32);
+ /* Toggle between 6/0 or 2/4 on split controllers */ + reg16 |= (config->sata_port_split << 5) & 0x20; + pci_write_config16(dev, 0x90, reg16); + /* Port enable */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f;