Attention is currently required from: Krystian Hebel, Martin L Roth, Michał Żygowski, Paul Menzel, Subrata Banik, Tarun Tuli.
Hello Krystian Hebel, Martin L Roth, Subrata Banik, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68987?usp=email
to look at the new patch set (#10).
The following approvals got outdated and were removed: Code-Review+2 by Krystian Hebel
Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash ......................................................................
soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in the SPI flash. New flashmap region is created for that purpose. The goal of caching is to reduce the dependency on CSME and the HECI IP LOAD command which may fail when the CSME is disabled, e.g. soft disabled by HECI command or HAP disabled. This change allows to keep PCIe 5.0 root ports functioning even if CSME/HECI is not functional.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port is functional after loading the HSPHY from cache.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f --- M Makefile.inc M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/hsphy.c M util/cbfstool/default-x86.fmd 5 files changed, 309 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/68987/10