Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42669 )
Change subject: mb/emulation/qemu-q35: Use common early SPI code ......................................................................
mb/emulation/qemu-q35: Use common early SPI code
Tested, it still boots. It is unknown whether this has any effect on emulated hardware, which is most likely not emulating SPI transfers.
Change-Id: I44397c46dc0715697ca8680f418888804e4ea7e4 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42669 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/mainboard/emulation/qemu-q35/bootblock.c 1 file changed, 2 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 3168f47..fafa03b 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -2,6 +2,7 @@
#include <device/pci_ops.h> #include <bootblock_common.h> +#include <southbridge/intel/common/early_spi.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <console/console.h>
@@ -37,20 +38,9 @@ die("You must run qemu for machine Q35 (-M q35)"); }
-static void enable_spi_prefetch(void) -{ - u8 reg8; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); -} - static void bootblock_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching();
/* Enable RCBA */ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA,