[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/tigerlake: Drop redundant PcieRpEnable

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Jeremy Compostella, Jeremy Soller, Michael Niewöhner, Nick Vaccaro, Nico Huber, Subrata Banik, Tim Crawford.

Hello Arthur Heymans, Jeremy Compostella, Jeremy Soller, Michael Niewöhner, Nicholas Sudsgaard, Nick Vaccaro, Subrata Banik, Tim Crawford, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/79920?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/tigerlake: Drop redundant PcieRpEnable
......................................................................

soc/intel/tigerlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infracture instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20
Signed-off-by: Nico Huber 
Signed-off-by: Nicholas Sudsgaard 
---
M src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/chronicler/overridetree.cb
M src/mainboard/google/volteer/variants/elemi/overridetree.cb
M src/mainboard/google/volteer/variants/voema/overridetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
M src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
M src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
M src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
M src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
M src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
M src/soc/intel/tigerlake/Makefile.mk
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
16 files changed, 20 insertions(+), 56 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/79920/3