Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30077
to look at the new patch set (#2).
Change subject: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports ......................................................................
sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports
The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root ports, all others have 8 [1]. The existing PCIe code assumed that all non-LP chipsets had 8 root ports, which meant that port 6 would not be considered the last root port on H81, so `root_port_commit_config()` would not run. Ultimately, while PCIe still worked on H81, all the root ports would remain enabled, even if disabled in the devicetree.
Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they are unused, and the MAX constant is incorrect.
Interestingly, this fixes an issue where GRUB is unable to halt the system.
Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree do indeed end up disabled.
[1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904.
Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Signed-off-by: Tristan Corrick tristan@corrick.kiwi --- M src/include/device/pci_ids.h M src/mainboard/asrock/h81m-hds/devicetree.cb M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c 5 files changed, 38 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30077/2