Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9349
-gerrit
commit 5dfac30903bb82fd3531bb49e5ec77937b1db42c Author: Julius Werner jwerner@chromium.org Date: Mon Oct 20 13:14:55 2014 -0700
rk3288: Change all SoC headers to <soc/headername.h> system
This patch is the start of a series to change all non-x86 SoC-specific headers to be included as <soc/header.h> instead of the old <soc/vendor/chip/header.h> or "header.h". It will add an include/soc/ directory under every src/soc/vendor/chip/ and append the .../include/ part of that to the global include path.
This matches the usage of <arch/header.h> for architecture-specific headers and had already been done for some headers on Tegra. It has the advantage that a source file which does not know the specific SoC used (e.g. Tegra files common for multiple chips, or a global include file) can still include SoC-specific headers and access macros/types defined there. It also makes the includes for mainboard files more readable, and reduces the chance to pull in a wrong header when copying mainboard sources to use a different-related SoC (e.g. using a Tegra124 mainboard as template for a Tegra132 one).
For easier maintainability, every SoC family is modified individually. This patch starts out by changing Rk3288. Also alphabetized headers in affected files since we touch them anyway.
BUG=None TEST=Whole series: compared binary images for Daisy, Nyan_Blaze, Rush_Ryu, Storm, Urara and Veyron_Pinky. Confirmed that they are byte-for-byte identical except for timestamps, hashes, and __LINE__ macro replacements. Compile-tested individual patches.
Change-Id: I4d74a0c56be278e591a9cf43f93e9900e41f4319 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 4ad8b6d2e0280428aa9742f0f7b723c00857334a Original-Change-Id: I415b8dbe735e572d4ae2cb1df62d66bcce386fff Original-Signed-off-by: Julius Werner jwerner@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/222025 --- src/arch/arm/include/arch/clock.h | 2 + src/arch/arm64/include/arch/clock.h | 2 + src/mainboard/google/veyron_pinky/board.h | 2 +- src/mainboard/google/veyron_pinky/boardid.c | 7 +- src/mainboard/google/veyron_pinky/bootblock.c | 12 +- src/mainboard/google/veyron_pinky/chromeos.c | 2 +- src/mainboard/google/veyron_pinky/mainboard.c | 24 +-- src/mainboard/google/veyron_pinky/memlayout.ld | 2 +- src/mainboard/google/veyron_pinky/reset.c | 2 +- src/mainboard/google/veyron_pinky/romstage.c | 25 +-- src/mainboard/google/veyron_pinky/sdram_configs.c | 6 +- src/soc/rockchip/rk3288/Makefile.inc | 2 + src/soc/rockchip/rk3288/addressmap.h | 103 ---------- src/soc/rockchip/rk3288/bootblock.c | 8 +- src/soc/rockchip/rk3288/cbmem.c | 5 +- src/soc/rockchip/rk3288/clock.c | 16 +- src/soc/rockchip/rk3288/clock.h | 48 ----- src/soc/rockchip/rk3288/gpio.c | 9 +- src/soc/rockchip/rk3288/gpio.h | 77 -------- src/soc/rockchip/rk3288/grf.h | 220 ---------------------- src/soc/rockchip/rk3288/i2c.c | 20 +- src/soc/rockchip/rk3288/i2c.h | 26 --- src/soc/rockchip/rk3288/include/soc/addressmap.h | 103 ++++++++++ src/soc/rockchip/rk3288/include/soc/clock.h | 48 +++++ src/soc/rockchip/rk3288/include/soc/gpio.h | 76 ++++++++ src/soc/rockchip/rk3288/include/soc/grf.h | 220 ++++++++++++++++++++++ src/soc/rockchip/rk3288/include/soc/i2c.h | 26 +++ src/soc/rockchip/rk3288/include/soc/memlayout.ld | 49 +++++ src/soc/rockchip/rk3288/include/soc/pmu.h | 78 ++++++++ src/soc/rockchip/rk3288/include/soc/pwm.h | 26 +++ src/soc/rockchip/rk3288/include/soc/rk808.h | 27 +++ src/soc/rockchip/rk3288/include/soc/sdram.h | 102 ++++++++++ src/soc/rockchip/rk3288/include/soc/soc.h | 38 ++++ src/soc/rockchip/rk3288/include/soc/spi.h | 204 ++++++++++++++++++++ src/soc/rockchip/rk3288/include/soc/timer.h | 45 +++++ src/soc/rockchip/rk3288/include/soc/tsadc.h | 25 +++ src/soc/rockchip/rk3288/media.c | 3 +- src/soc/rockchip/rk3288/memlayout.ld | 49 ----- src/soc/rockchip/rk3288/monotonic_timer.c | 6 +- src/soc/rockchip/rk3288/pmu.h | 77 -------- src/soc/rockchip/rk3288/pwm.c | 17 +- src/soc/rockchip/rk3288/pwm.h | 26 --- src/soc/rockchip/rk3288/rk808.c | 4 +- src/soc/rockchip/rk3288/rk808.h | 27 --- src/soc/rockchip/rk3288/sdram.c | 16 +- src/soc/rockchip/rk3288/sdram.h | 104 ---------- src/soc/rockchip/rk3288/soc.c | 17 +- src/soc/rockchip/rk3288/soc.h | 38 ---- src/soc/rockchip/rk3288/spi.c | 14 +- src/soc/rockchip/rk3288/spi.h | 204 -------------------- src/soc/rockchip/rk3288/timer.c | 5 +- src/soc/rockchip/rk3288/timer.h | 45 ----- src/soc/rockchip/rk3288/tsadc.c | 12 +- src/soc/rockchip/rk3288/tsadc.h | 25 --- src/soc/rockchip/rk3288/uart.c | 4 +- 55 files changed, 1193 insertions(+), 1187 deletions(-)
diff --git a/src/arch/arm/include/arch/clock.h b/src/arch/arm/include/arch/clock.h index a11fbd4..939aa20 100644 --- a/src/arch/arm/include/arch/clock.h +++ b/src/arch/arm/include/arch/clock.h @@ -20,6 +20,8 @@ #ifndef __ARM_CLOCK_H_ #define __ARM_CLOCK_H_
+#include <types.h> + void set_cntfrq(uint32_t);
#endif //__ARM_CLOCK_H_ diff --git a/src/arch/arm64/include/arch/clock.h b/src/arch/arm64/include/arch/clock.h index a11fbd4..939aa20 100644 --- a/src/arch/arm64/include/arch/clock.h +++ b/src/arch/arm64/include/arch/clock.h @@ -20,6 +20,8 @@ #ifndef __ARM_CLOCK_H_ #define __ARM_CLOCK_H_
+#include <types.h> + void set_cntfrq(uint32_t);
#endif //__ARM_CLOCK_H_ diff --git a/src/mainboard/google/veyron_pinky/board.h b/src/mainboard/google/veyron_pinky/board.h index 2ffa9cf..8d452c8 100644 --- a/src/mainboard/google/veyron_pinky/board.h +++ b/src/mainboard/google/veyron_pinky/board.h @@ -21,7 +21,7 @@ #define __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H
#include <boardid.h> -#include <soc/rockchip/rk3288/gpio.h> +#include <soc/gpio.h>
#define PMIC_BUS 0
diff --git a/src/mainboard/google/veyron_pinky/boardid.c b/src/mainboard/google/veyron_pinky/boardid.c index ca446a1..01e92a3 100644 --- a/src/mainboard/google/veyron_pinky/boardid.c +++ b/src/mainboard/google/veyron_pinky/boardid.c @@ -17,11 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <stdlib.h> -#include <console/console.h> -#include <soc/rockchip/rk3288/gpio.h> - #include <boardid.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <stdlib.h>
uint8_t board_id(void) { diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index a66d748..b34199d 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -20,12 +20,12 @@
#include <arch/io.h> #include <bootblock_common.h> -#include <soc/rockchip/rk3288/grf.h> -#include <soc/rockchip/rk3288/spi.h> -#include <soc/rockchip/rk3288/rk808.h> -#include <soc/rockchip/rk3288/clock.h> -#include <soc/rockchip/rk3288/pmu.h> -#include <soc/rockchip/rk3288/i2c.h> +#include <soc/clock.h> +#include <soc/i2c.h> +#include <soc/grf.h> +#include <soc/pmu.h> +#include <soc/rk808.h> +#include <soc/spi.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "board.h" diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c index 827b004..30cd277 100644 --- a/src/mainboard/google/veyron_pinky/chromeos.c +++ b/src/mainboard/google/veyron_pinky/chromeos.c @@ -21,9 +21,9 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> +#include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/rockchip/rk3288/gpio.h>
#include "board.h"
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c index 19d6675..a8cc3c3 100644 --- a/src/mainboard/google/veyron_pinky/mainboard.c +++ b/src/mainboard/google/veyron_pinky/mainboard.c @@ -17,22 +17,24 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <console/console.h> -#include <device/device.h> #include <arch/cache.h> +#include <arch/io.h> +#include <console/console.h> #include <delay.h> +#include <device/device.h> #include <edid.h> -#include <symbols.h> -#include <vbe.h> #include <boot/coreboot_tables.h> #include <device/i2c.h> -#include <soc/rockchip/rk3288/gpio.h> -#include <soc/rockchip/rk3288/soc.h> -#include <soc/rockchip/rk3288/pmu.h> -#include <soc/rockchip/rk3288/clock.h> -#include <soc/rockchip/rk3288/rk808.h> -#include <soc/rockchip/rk3288/spi.h> -#include <soc/rockchip/rk3288/i2c.h> +#include <soc/gpio.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/pmu.h> +#include <soc/clock.h> +#include <soc/rk808.h> +#include <soc/spi.h> +#include <soc/i2c.h> +#include <symbols.h> +#include <vbe.h>
#include "board.h"
diff --git a/src/mainboard/google/veyron_pinky/memlayout.ld b/src/mainboard/google/veyron_pinky/memlayout.ld index a8b7465..ead7f47 100644 --- a/src/mainboard/google/veyron_pinky/memlayout.ld +++ b/src/mainboard/google/veyron_pinky/memlayout.ld @@ -1 +1 @@ -#include <soc/rockchip/rk3288/memlayout.ld> +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/veyron_pinky/reset.c b/src/mainboard/google/veyron_pinky/reset.c index 45c28b2..a2777f8 100644 --- a/src/mainboard/google/veyron_pinky/reset.c +++ b/src/mainboard/google/veyron_pinky/reset.c @@ -18,7 +18,7 @@ */
#include <arch/io.h> -#include <soc/rockchip/rk3288/gpio.h> +#include <soc/gpio.h> #include <reset.h>
#include "board.h" diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index ab7903c..38166ed 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -17,26 +17,27 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <types.h> +#include <arch/cache.h> +#include <arch/exception.h> #include <arch/stages.h> #include <armv7.h> +#include <assert.h> #include <cbfs.h> -#include <console/console.h> #include <cbmem.h> +#include <console/console.h> #include <delay.h> #include <program_loading.h> -#include <timestamp.h> -#include <arch/cache.h> -#include <arch/exception.h> +#include <soc/sdram.h> +#include <soc/clock.h> +#include <soc/pwm.h> +#include <soc/grf.h> +#include <soc/tsadc.h> #include <stdlib.h> -#include <assert.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/rockchip/rk3288/sdram.h> -#include <soc/rockchip/rk3288/clock.h> -#include <soc/rockchip/rk3288/pwm.h> -#include <soc/rockchip/rk3288/grf.h> -#include <soc/rockchip/rk3288/tsadc.h> #include <symbols.h> +#include <timestamp.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + #include "timer.h"
static void regulate_vdd_log(unsigned int mv) diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c index cc29de0..1a331ce 100644 --- a/src/mainboard/google/veyron_pinky/sdram_configs.c +++ b/src/mainboard/google/veyron_pinky/sdram_configs.c @@ -17,11 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <arch/io.h> +#include <console/console.h> +#include <soc/sdram.h> +#include <soc/gpio.h> #include <string.h> #include <types.h> -#include <console/console.h> -#include <soc/rockchip/rk3288/sdram.h> -#include <soc/rockchip/rk3288/gpio.h>
static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 076f0dc..9ad0f6e 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -68,6 +68,8 @@ ramstage-y += rk808.c ramstage-y += pwm.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+INCLUDES += -Isrc/soc/rockchip/rk3288/include/ + $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@
diff --git a/src/soc/rockchip/rk3288/addressmap.h b/src/soc/rockchip/rk3288/addressmap.h deleted file mode 100644 index aea3bc0..0000000 --- a/src/soc/rockchip/rk3288/addressmap.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ -#define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ - -#define SDMMC1_BASE 0xFF0C0000 -#define SDMMC0_BASE 0xFF0D0000 -#define EMMC_BASE 0xFF0F0000 -#define SARADC_BASE 0xFF100000 - -#define SPI0_BASE 0xFF110000 -#define SPI1_BASE 0xFF120000 -#define SPI2_BASE 0xFF130000 - -#define I2C1_BASE 0xFF140000 -#define I2C3_BASE 0xFF150000 -#define I2C4_BASE 0xFF160000 -#define I2C5_BASE 0xFF170000 -#define UART0_BASE 0xFF180000 -#define UART1_BASE 0xFF190000 -#define DMAC_PERI_BASE 0xFF250000 -#define TSADC_BASE 0xFF280000 - -#define NANDC0_BASE 0xFF400000 -#define NANDC1_BASE 0xFF410000 - -#define USB_HOST0_EHCI_BASE 0xFF500000 -#define USB_HOST0_OHCI_BASE 0xFF520000 -#define USB_HOST1_BASE 0xFF540000 -#define USB_OTG_BASE 0xFF580000 - -#define DMAC_BUS_BASE 0xFF600000 - -#define DDR_PCTL0_BASE 0xFF610000 -#define DDR_PCTL1_BASE 0xFF630000 -#define DDR_PUBL0_BASE 0xFF620000 -#define DDR_PUBL1_BASE 0xFF640000 - -#define I2C0_BASE 0xFF650000 -#define I2C2_BASE 0xFF660000 -#define DW_PWM0123_BASE 0xFF670000 -#define RK_PWM0123_BASE 0xFF680000 -#define UART2_BASE 0xFF690000 -#define TIMER0_BASE 0xFF6B0000 - -#define SRAM_BASE 0xFF700000 -#define PMU_BASE 0xFF730000 -#define GRF_SECURE_BASE 0xFF740000 -#define GPIO0_BASE 0xFF750000 -#define CRU_BASE 0xFF760000 -#define GRF_BASE 0xFF770000 -#define GPIO1_BASE 0xFF780000 -#define GPIO2_BASE 0xFF790000 -#define GPIO3_BASE 0xFF7A0000 -#define GPIO4_BASE 0xFF7B0000 -#define GPIO5_BASE 0xFF7C0000 -#define GPIO6_BASE 0xFF7D0000 -#define GPIO7_BASE 0xFF7E0000 -#define GPIO8_BASE 0xFF7F0000 - -#define TIMER6_BASE 0xFF810000 -#define TIMER7_BASE 0xFF810020 - -#define VOP_BIG_BASE 0xFF930000 -#define HDMI_TX_BASE 0xFF980000 -#define DMACS_BUS_BASE 0xFFB20000 - -#define SERVICE_CORE_BASE 0xFFA80000 -#define SERVICE_DMA_BASE 0xFFA90000 -#define SERVICE_GPU_BASE 0xFFAA0000 -#define SERVICE_PERI_BASE 0xFFAB0000 -#define SERVICE_BUS_BASE 0xFFAC0000 -#define SERVICE_VIO_BASE 0xFFAD0000 -#define SERVICE_VPU_BASE 0xFFAE0000 -#define SERVICE_HEVC_BASE 0xFFAF0000 - -#define EFUSE_BASE 0xFFB40000 - -#define CORE_GICD_BASE 0xFFC01000 -#define CORE_GICC_BASE 0xFFC02000 -#define CPU_AXI_BUS_BASE 0xFFE00000 - -#define BOOT_ROM_BASE 0xFFFF0000 -#define BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0) - -#endif /* __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ */ diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index b2f5bd9..26a6569 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -21,11 +21,11 @@ #include <arch/io.h> #include <bootblock_common.h> #include <console/console.h> -#include <soc/rockchip/rk3288/grf.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/grf.h> +#include <soc/timer.h> #include <symbols.h> -#include "addressmap.h" -#include "timer.h" -#include "clock.h"
static void bootblock_cpu_init(void) { diff --git a/src/soc/rockchip/rk3288/cbmem.c b/src/soc/rockchip/rk3288/cbmem.c index dc1e0aa..1c3a902 100644 --- a/src/soc/rockchip/rk3288/cbmem.c +++ b/src/soc/rockchip/rk3288/cbmem.c @@ -17,9 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <stddef.h> #include <cbmem.h> -#include "soc.h" +#include <soc/soc.h> +#include <stddef.h> + void *cbmem_top(void) { return (void *)(get_fb_base_kb()*KiB); diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 5ad431c..d95257f 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <assert.h> -#include <stdlib.h> #include <arch/io.h> -#include <stdint.h> -#include <string.h> +#include <assert.h> #include <console/console.h> #include <delay.h> -#include "clock.h" -#include "grf.h" -#include "addressmap.h" -#include "soc.h" +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h>
struct pll_div { u32 nr; diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h deleted file mode 100644 index e2e8f3f..0000000 --- a/src/soc/rockchip/rk3288/clock.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_CLOCK_H__ -#define __SOC_ROCKCHIP_RK3288_CLOCK_H__ - -#include "addressmap.h" - -#define OSC_HZ (24*MHz) - -#define APLL_HZ (1800*MHz) -#define GPLL_HZ (594*MHz) -#define CPLL_HZ (384*MHz) - -#define PD_BUS_ACLK_HZ (148500*KHz) -#define PD_BUS_HCLK_HZ (148500*KHz) -#define PD_BUS_PCLK_HZ (74250*KHz) - -#define PERI_ACLK_HZ (148500*KHz) -#define PERI_HCLK_HZ (148500*KHz) -#define PERI_PCLK_HZ (74250*KHz) - -void rkclk_init(void); -void rkclk_configure_spi(unsigned int bus, unsigned int hz); -void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); -void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n); -void rkclk_configure_ddr(unsigned int hz); -void rkclk_configure_i2s(unsigned int hz); -void rkclk_configure_cpu(void); -void rkclk_configure_tsadc(unsigned int hz); - -#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 2d1ae15..c3784ec 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -17,12 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <console/console.h> #include <arch/io.h> +#include <console/console.h> +#include <soc/soc.h> +#include <soc/gpio.h> +#include <soc/grf.h> +#include <soc/pmu.h> #include <stdlib.h> -#include "soc.h" -#include "gpio.h" -#include "pmu.h"
struct rk3288_gpio_regs *gpio_port[] = { (struct rk3288_gpio_regs *)0xff750000, diff --git a/src/soc/rockchip/rk3288/gpio.h b/src/soc/rockchip/rk3288/gpio.h deleted file mode 100644 index 7049ddf..0000000 --- a/src/soc/rockchip/rk3288/gpio.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_GPIO_H__ -#define __SOC_ROCKCHIP_RK3288_GPIO_H__ - -#include "addressmap.h" -#include "grf.h" - -#define GPIO(p, b, i) ((gpio_t){.port = p, .bank = GPIO_##b, .idx = i}) - -struct rk3288_gpio_regs { - u32 swporta_dr; - u32 swporta_ddr; - u32 reserved0[(0x30 - 0x08) / 4]; - u32 inten; - u32 intmask; - u32 inttype_level; - u32 int_polarity; - u32 int_status; - u32 int_rawstatus; - u32 debounce; - u32 porta_eoi; - u32 ext_porta; - u32 reserved1[(0x60 - 0x54) / 4]; - u32 ls_sync; -}; -check_member(rk3288_gpio_regs, ls_sync, 0x60); - -typedef union { - u32 raw; - struct { - u16 port; - union { - struct { - u16 num:5; - u16 :11; - }; - struct { - u16 idx:3; - u16 bank:2; - u16 :11; - }; - }; - }; -} gpio_t; - -enum { - GPIO_A = 0, - GPIO_B, - GPIO_C, - GPIO_D, -}; - -void gpio_input(gpio_t gpio); -void gpio_input_pulldown(gpio_t gpio); -void gpio_input_pullup(gpio_t gpio); -void gpio_output(gpio_t gpio, int value); -int gpio_get_in_value(gpio_t gpio); - -#endif /* _ASM_ROCKCHIP_GPIO_H_ */ diff --git a/src/soc/rockchip/rk3288/grf.h b/src/soc/rockchip/rk3288/grf.h deleted file mode 100644 index e84359b..0000000 --- a/src/soc/rockchip/rk3288/grf.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_GRF_H__ -#define __SOC_ROCKCHIP_RK3288_GRF_H__ - -#include <types.h> -#include "addressmap.h" -#include "soc.h" - -struct rk3288_grf_gpio_lh { - u32 l; - u32 h; -}; -check_member(rk3288_grf_gpio_lh, h, 0x4); - -struct rk3288_grf_regs { - u32 reserved[3]; - union { - u32 gpio1d_iomux; - u32 iomux_lcdc; - }; - u32 gpio2a_iomux; - u32 gpio2b_iomux; - union { - u32 gpio2c_iomux; - u32 iomux_i2c3; - }; - u32 reserved2; - union { - u32 gpio3a_iomux; - u32 iomux_emmcdata; - }; - union { - u32 gpio3b_iomux; - u32 iomux_emmcpwren; - }; - union { - u32 gpio3c_iomux; - u32 iomux_emmccmd; - }; - u32 gpio3dl_iomux; - u32 gpio3dh_iomux; - u32 gpio4al_iomux; - u32 gpio4ah_iomux; - u32 gpio4bl_iomux; - u32 reserved3; - u32 gpio4c_iomux; - u32 gpio4d_iomux; - u32 reserved4; - union { - u32 gpio5b_iomux; - u32 iomux_spi0; - }; - u32 gpio5c_iomux; - u32 reserved5; - union { - u32 gpio6a_iomux; - u32 iomux_i2s; - }; - union { - u32 gpio6b_iomux; - u32 iomux_i2c2; - u32 iomux_i2sclk; - }; - union { - u32 gpio6c_iomux; - u32 iomux_sdmmc0; - }; - u32 reserved6; - union { - u32 gpio7a_iomux; - u32 iomux_pwm0; - u32 iomux_pwm1; - }; - u32 gpio7b_iomux; - union { - u32 gpio7cl_iomux; - u32 iomux_i2c5sda; - u32 iomux_i2c4; - }; - union { - u32 gpio7ch_iomux; - u32 iomux_uart2; - u32 iomux_i2c5scl; - }; - u32 reserved7; - union { - u32 gpio8a_iomux; - u32 iomux_spi2csclk; - u32 iomux_i2c1; - }; - union { - u32 gpio8b_iomux; - u32 iomux_spi2txrx; - }; - u32 reserved8[30]; - struct rk3288_grf_gpio_lh gpio_sr[8]; - u32 gpio1_p[8][4]; - u32 gpio1_e[8][4]; - u32 gpio_smt; - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5; - u32 soc_con6; - u32 soc_con7; - u32 soc_con8; - u32 soc_con9; - u32 soc_con10; - u32 soc_con11; - u32 soc_con12; - u32 soc_con13; - u32 soc_con14; - u32 soc_status[22]; - u32 reserved9[2]; - u32 peridmac_con[4]; - u32 ddrc0_con0; - u32 ddrc1_con0; - u32 cpu_con[5]; - u32 reserved10[3]; - u32 cpu_status0; - u32 reserved11; - u32 uoc0_con[5]; - u32 uoc1_con[5]; - u32 uoc2_con[4]; - u32 uoc3_con[2]; - u32 uoc4_con[2]; - u32 pvtm_con[3]; - u32 pvtm_status[3]; - u32 io_vsel; - u32 saradc_testbit; - u32 tsadc_testbit_l; - u32 tsadc_testbit_h; - u32 os_reg[4]; - u32 reserved12; - u32 soc_con15; - u32 soc_con16; -}; -check_member(rk3288_grf_regs, soc_con16, 0x3a8); - -struct rk3288_sgrf_regs { - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5; - u32 reserved1[(0x20-0x18)/4]; - u32 busdmac_con[2]; - u32 reserved2[(0x40-0x28)/4]; - u32 cpu_con[3]; - u32 reserved3[(0x50-0x4c)/4]; - u32 soc_con6; - u32 soc_con7; - u32 soc_con8; - u32 soc_con9; - u32 soc_con10; - u32 soc_con11; - u32 soc_con12; - u32 soc_con13; - u32 soc_con14; - u32 soc_con15; - u32 soc_con16; - u32 soc_con17; - u32 soc_con18; - u32 soc_con19; - u32 soc_con20; - u32 soc_con21; - u32 reserved4[(0x100-0x90)/4]; - u32 soc_status[2]; - u32 reserved5[(0x120-0x108)/4]; - u32 fast_boot_addr; -}; -check_member(rk3288_sgrf_regs, fast_boot_addr, 0x0120); - -static struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE; -static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE; - -#define IOMUX_I2C1 RK_CLRSETBITS(3 << 10 | 3 << 8, 1 << 10 | 1 << 8) -#define IOMUX_I2C2 RK_SETBITS(1 << 4 | 1 << 2) -#define IOMUX_I2C3 RK_SETBITS(1 << 2 | 1 << 0) -#define IOMUX_I2C4 RK_SETBITS(1 << 8 | 1 << 4) -#define IOMUX_I2C5SDA RK_CLRSETBITS(3 << 12, 1 << 12) -#define IOMUX_I2C5SCL RK_CLRSETBITS(3 << 0, 1 << 0) -#define IOMUX_SPI0 RK_CLRSETBITS(0xff << 8, 1 << 14 | 1 << 12 | \ - 1 << 10 | 1 << 8) -#define IOMUX_SPI2_CSCLK RK_CLRSETBITS(3 << 14 | 3 << 12, 1 << 14 | 1 << 12) -#define IOMUX_SPI2_TXRX RK_CLRSETBITS(3 << 2 | 3 << 0, 1 << 2 | 1 << 0) -#define IOMUX_I2S RK_SETBITS(1 << 8 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) -#define IOMUX_I2SCLK RK_SETBITS(1 << 0) -#define IOMUX_UART2 RK_CLRSETBITS(7 << 12 | 3 << 8, 1 << 12 | 1 << 8) -#define IOMUX_LCDC RK_SETBITS(1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) -#define IOMUX_SDMMC0 RK_CLRSETBITS(0x17ff, 1 << 12 | 1 << 10 | 1 << 8 |\ - 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) -#define IOMUX_EMMCDATA RK_CLRSETBITS(0xffff, 2 << 14 | 2 << 12 | 2 << 10 |\ - 2 << 8 | 2 << 6 | 2 << 4 |\ - 2 << 2 | 2 << 0) -#define IOMUX_EMMCPWREN RK_CLRSETBITS(0x3 << 2, 0x2 << 2) -#define IOMUX_EMMCCMD RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0) -#define IOMUX_PWM1 RK_SETBITS(1 << 2) -#endif diff --git a/src/soc/rockchip/rk3288/i2c.c b/src/soc/rockchip/rk3288/i2c.c index eb480a7..d69bb7c 100644 --- a/src/soc/rockchip/rk3288/i2c.c +++ b/src/soc/rockchip/rk3288/i2c.c @@ -17,21 +17,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <console/console.h> #include <arch/io.h> -#include <stdlib.h> #include <assert.h> - -#include <delay.h> #include <cbfs.h> -#include <string.h> +#include <console/console.h> +#include <delay.h> #include <device/i2c.h> - -#include "addressmap.h" -#include "grf.h" -#include "soc.h" -#include "i2c.h" -#include "clock.h" +#include <soc/addressmap.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/i2c.h> +#include <soc/clock.h> +#include <stdlib.h> +#include <string.h>
#define RETRY_COUNT 3 /* 100000us = 100ms */ diff --git a/src/soc/rockchip/rk3288/i2c.h b/src/soc/rockchip/rk3288/i2c.h deleted file mode 100644 index 84d9b75..0000000 --- a/src/soc/rockchip/rk3288/i2c.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_I2C_H__ -#define __SOC_ROCKCHIP_RK3288_I2C_H__ - -void i2c_init(unsigned int bus, unsigned int hz); - -#endif - diff --git a/src/soc/rockchip/rk3288/include/soc/addressmap.h b/src/soc/rockchip/rk3288/include/soc/addressmap.h new file mode 100644 index 0000000..aea3bc0 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/addressmap.h @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ +#define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ + +#define SDMMC1_BASE 0xFF0C0000 +#define SDMMC0_BASE 0xFF0D0000 +#define EMMC_BASE 0xFF0F0000 +#define SARADC_BASE 0xFF100000 + +#define SPI0_BASE 0xFF110000 +#define SPI1_BASE 0xFF120000 +#define SPI2_BASE 0xFF130000 + +#define I2C1_BASE 0xFF140000 +#define I2C3_BASE 0xFF150000 +#define I2C4_BASE 0xFF160000 +#define I2C5_BASE 0xFF170000 +#define UART0_BASE 0xFF180000 +#define UART1_BASE 0xFF190000 +#define DMAC_PERI_BASE 0xFF250000 +#define TSADC_BASE 0xFF280000 + +#define NANDC0_BASE 0xFF400000 +#define NANDC1_BASE 0xFF410000 + +#define USB_HOST0_EHCI_BASE 0xFF500000 +#define USB_HOST0_OHCI_BASE 0xFF520000 +#define USB_HOST1_BASE 0xFF540000 +#define USB_OTG_BASE 0xFF580000 + +#define DMAC_BUS_BASE 0xFF600000 + +#define DDR_PCTL0_BASE 0xFF610000 +#define DDR_PCTL1_BASE 0xFF630000 +#define DDR_PUBL0_BASE 0xFF620000 +#define DDR_PUBL1_BASE 0xFF640000 + +#define I2C0_BASE 0xFF650000 +#define I2C2_BASE 0xFF660000 +#define DW_PWM0123_BASE 0xFF670000 +#define RK_PWM0123_BASE 0xFF680000 +#define UART2_BASE 0xFF690000 +#define TIMER0_BASE 0xFF6B0000 + +#define SRAM_BASE 0xFF700000 +#define PMU_BASE 0xFF730000 +#define GRF_SECURE_BASE 0xFF740000 +#define GPIO0_BASE 0xFF750000 +#define CRU_BASE 0xFF760000 +#define GRF_BASE 0xFF770000 +#define GPIO1_BASE 0xFF780000 +#define GPIO2_BASE 0xFF790000 +#define GPIO3_BASE 0xFF7A0000 +#define GPIO4_BASE 0xFF7B0000 +#define GPIO5_BASE 0xFF7C0000 +#define GPIO6_BASE 0xFF7D0000 +#define GPIO7_BASE 0xFF7E0000 +#define GPIO8_BASE 0xFF7F0000 + +#define TIMER6_BASE 0xFF810000 +#define TIMER7_BASE 0xFF810020 + +#define VOP_BIG_BASE 0xFF930000 +#define HDMI_TX_BASE 0xFF980000 +#define DMACS_BUS_BASE 0xFFB20000 + +#define SERVICE_CORE_BASE 0xFFA80000 +#define SERVICE_DMA_BASE 0xFFA90000 +#define SERVICE_GPU_BASE 0xFFAA0000 +#define SERVICE_PERI_BASE 0xFFAB0000 +#define SERVICE_BUS_BASE 0xFFAC0000 +#define SERVICE_VIO_BASE 0xFFAD0000 +#define SERVICE_VPU_BASE 0xFFAE0000 +#define SERVICE_HEVC_BASE 0xFFAF0000 + +#define EFUSE_BASE 0xFFB40000 + +#define CORE_GICD_BASE 0xFFC01000 +#define CORE_GICC_BASE 0xFFC02000 +#define CPU_AXI_BUS_BASE 0xFFE00000 + +#define BOOT_ROM_BASE 0xFFFF0000 +#define BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0) + +#endif /* __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ */ diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h new file mode 100644 index 0000000..d11c6ec --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_CLOCK_H__ +#define __SOC_ROCKCHIP_RK3288_CLOCK_H__ + +#include <soc/addressmap.h> + +#define OSC_HZ (24*MHz) + +#define APLL_HZ (1800*MHz) +#define GPLL_HZ (594*MHz) +#define CPLL_HZ (384*MHz) + +#define PD_BUS_ACLK_HZ (148500*KHz) +#define PD_BUS_HCLK_HZ (148500*KHz) +#define PD_BUS_PCLK_HZ (74250*KHz) + +#define PERI_ACLK_HZ (148500*KHz) +#define PERI_HCLK_HZ (148500*KHz) +#define PERI_PCLK_HZ (74250*KHz) + +void rkclk_init(void); +void rkclk_configure_spi(unsigned int bus, unsigned int hz); +void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); +void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n); +void rkclk_configure_ddr(unsigned int hz); +void rkclk_configure_i2s(unsigned int hz); +void rkclk_configure_cpu(void); +void rkclk_configure_tsadc(unsigned int hz); + +#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3288/include/soc/gpio.h b/src/soc/rockchip/rk3288/include/soc/gpio.h new file mode 100644 index 0000000..c459de9 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/gpio.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_GPIO_H__ +#define __SOC_ROCKCHIP_RK3288_GPIO_H__ + +#include <types.h> + +#define GPIO(p, b, i) ((gpio_t){.port = p, .bank = GPIO_##b, .idx = i}) + +struct rk3288_gpio_regs { + u32 swporta_dr; + u32 swporta_ddr; + u32 reserved0[(0x30 - 0x08) / 4]; + u32 inten; + u32 intmask; + u32 inttype_level; + u32 int_polarity; + u32 int_status; + u32 int_rawstatus; + u32 debounce; + u32 porta_eoi; + u32 ext_porta; + u32 reserved1[(0x60 - 0x54) / 4]; + u32 ls_sync; +}; +check_member(rk3288_gpio_regs, ls_sync, 0x60); + +typedef union { + u32 raw; + struct { + u16 port; + union { + struct { + u16 num:5; + u16 :11; + }; + struct { + u16 idx:3; + u16 bank:2; + u16 :11; + }; + }; + }; +} gpio_t; + +enum { + GPIO_A = 0, + GPIO_B, + GPIO_C, + GPIO_D, +}; + +void gpio_input(gpio_t gpio); +void gpio_input_pulldown(gpio_t gpio); +void gpio_input_pullup(gpio_t gpio); +void gpio_output(gpio_t gpio, int value); +int gpio_get_in_value(gpio_t gpio); + +#endif /* _ASM_ROCKCHIP_GPIO_H_ */ diff --git a/src/soc/rockchip/rk3288/include/soc/grf.h b/src/soc/rockchip/rk3288/include/soc/grf.h new file mode 100644 index 0000000..8325638 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/grf.h @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_GRF_H__ +#define __SOC_ROCKCHIP_RK3288_GRF_H__ + +#include <soc/addressmap.h> +#include <soc/soc.h> +#include <types.h> + +struct rk3288_grf_gpio_lh { + u32 l; + u32 h; +}; +check_member(rk3288_grf_gpio_lh, h, 0x4); + +struct rk3288_grf_regs { + u32 reserved[3]; + union { + u32 gpio1d_iomux; + u32 iomux_lcdc; + }; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + union { + u32 gpio2c_iomux; + u32 iomux_i2c3; + }; + u32 reserved2; + union { + u32 gpio3a_iomux; + u32 iomux_emmcdata; + }; + union { + u32 gpio3b_iomux; + u32 iomux_emmcpwren; + }; + union { + u32 gpio3c_iomux; + u32 iomux_emmccmd; + }; + u32 gpio3dl_iomux; + u32 gpio3dh_iomux; + u32 gpio4al_iomux; + u32 gpio4ah_iomux; + u32 gpio4bl_iomux; + u32 reserved3; + u32 gpio4c_iomux; + u32 gpio4d_iomux; + u32 reserved4; + union { + u32 gpio5b_iomux; + u32 iomux_spi0; + }; + u32 gpio5c_iomux; + u32 reserved5; + union { + u32 gpio6a_iomux; + u32 iomux_i2s; + }; + union { + u32 gpio6b_iomux; + u32 iomux_i2c2; + u32 iomux_i2sclk; + }; + union { + u32 gpio6c_iomux; + u32 iomux_sdmmc0; + }; + u32 reserved6; + union { + u32 gpio7a_iomux; + u32 iomux_pwm0; + u32 iomux_pwm1; + }; + u32 gpio7b_iomux; + union { + u32 gpio7cl_iomux; + u32 iomux_i2c5sda; + u32 iomux_i2c4; + }; + union { + u32 gpio7ch_iomux; + u32 iomux_uart2; + u32 iomux_i2c5scl; + }; + u32 reserved7; + union { + u32 gpio8a_iomux; + u32 iomux_spi2csclk; + u32 iomux_i2c1; + }; + union { + u32 gpio8b_iomux; + u32 iomux_spi2txrx; + }; + u32 reserved8[30]; + struct rk3288_grf_gpio_lh gpio_sr[8]; + u32 gpio1_p[8][4]; + u32 gpio1_e[8][4]; + u32 gpio_smt; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_status[22]; + u32 reserved9[2]; + u32 peridmac_con[4]; + u32 ddrc0_con0; + u32 ddrc1_con0; + u32 cpu_con[5]; + u32 reserved10[3]; + u32 cpu_status0; + u32 reserved11; + u32 uoc0_con[5]; + u32 uoc1_con[5]; + u32 uoc2_con[4]; + u32 uoc3_con[2]; + u32 uoc4_con[2]; + u32 pvtm_con[3]; + u32 pvtm_status[3]; + u32 io_vsel; + u32 saradc_testbit; + u32 tsadc_testbit_l; + u32 tsadc_testbit_h; + u32 os_reg[4]; + u32 reserved12; + u32 soc_con15; + u32 soc_con16; +}; +check_member(rk3288_grf_regs, soc_con16, 0x3a8); + +struct rk3288_sgrf_regs { + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 reserved1[(0x20-0x18)/4]; + u32 busdmac_con[2]; + u32 reserved2[(0x40-0x28)/4]; + u32 cpu_con[3]; + u32 reserved3[(0x50-0x4c)/4]; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 soc_con16; + u32 soc_con17; + u32 soc_con18; + u32 soc_con19; + u32 soc_con20; + u32 soc_con21; + u32 reserved4[(0x100-0x90)/4]; + u32 soc_status[2]; + u32 reserved5[(0x120-0x108)/4]; + u32 fast_boot_addr; +}; +check_member(rk3288_sgrf_regs, fast_boot_addr, 0x0120); + +static struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE; +static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE; + +#define IOMUX_I2C1 RK_CLRSETBITS(3 << 10 | 3 << 8, 1 << 10 | 1 << 8) +#define IOMUX_I2C2 RK_SETBITS(1 << 4 | 1 << 2) +#define IOMUX_I2C3 RK_SETBITS(1 << 2 | 1 << 0) +#define IOMUX_I2C4 RK_SETBITS(1 << 8 | 1 << 4) +#define IOMUX_I2C5SDA RK_CLRSETBITS(3 << 12, 1 << 12) +#define IOMUX_I2C5SCL RK_CLRSETBITS(3 << 0, 1 << 0) +#define IOMUX_SPI0 RK_CLRSETBITS(0xff << 8, 1 << 14 | 1 << 12 | \ + 1 << 10 | 1 << 8) +#define IOMUX_SPI2_CSCLK RK_CLRSETBITS(3 << 14 | 3 << 12, 1 << 14 | 1 << 12) +#define IOMUX_SPI2_TXRX RK_CLRSETBITS(3 << 2 | 3 << 0, 1 << 2 | 1 << 0) +#define IOMUX_I2S RK_SETBITS(1 << 8 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) +#define IOMUX_I2SCLK RK_SETBITS(1 << 0) +#define IOMUX_UART2 RK_CLRSETBITS(7 << 12 | 3 << 8, 1 << 12 | 1 << 8) +#define IOMUX_LCDC RK_SETBITS(1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) +#define IOMUX_SDMMC0 RK_CLRSETBITS(0x17ff, 1 << 12 | 1 << 10 | 1 << 8 |\ + 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) +#define IOMUX_EMMCDATA RK_CLRSETBITS(0xffff, 2 << 14 | 2 << 12 | 2 << 10 |\ + 2 << 8 | 2 << 6 | 2 << 4 |\ + 2 << 2 | 2 << 0) +#define IOMUX_EMMCPWREN RK_CLRSETBITS(0x3 << 2, 0x2 << 2) +#define IOMUX_EMMCCMD RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0) +#define IOMUX_PWM1 RK_SETBITS(1 << 2) +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/i2c.h b/src/soc/rockchip/rk3288/include/soc/i2c.h new file mode 100644 index 0000000..84d9b75 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/i2c.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_I2C_H__ +#define __SOC_ROCKCHIP_RK3288_I2C_H__ + +void i2c_init(unsigned int bus, unsigned int hz); + +#endif + diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld new file mode 100644 index 0000000..2ddb6a6 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> +#include <vendorcode/google/chromeos/memlayout.h> + +#include <arch/header.ld> + +/* Note: The BootROM will jump to 0xFF704004 after loading bootblock, + * so the bootblock loading address must be at 0xFF704004. + */ +SECTIONS +{ + DRAM_START(0x00000000) + RAMSTAGE(0x00200000, 128K) + POSTRAM_CBFS_CACHE(0x01000000, 1M) + DMA_COHERENT(0x10000000, 2M) + + SRAM_START(0xFF700000) + TTB(0xFF700000, 16K) + BOOTBLOCK(0xFF704004, 15K - 4) + TTB_SUBTABLES(0xFF707c00, 1K) + VBOOT2_WORK(0xFF708000, 16K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K) + PRERAM_CBFS_CACHE(0xFF716000, 4K) + STACK(0xFF717000, 4K) + SRAM_END(0xFF718000) + + /* 4K of special SRAM in PMU power domain. Careful: only supports 32-bit + * wide write accesses! Only use with MMU and writeback mapping. */ + SYMBOL(pmu_sram, 0xFF720000) + SYMBOL(epmu_sram, 0xFF721000) +} diff --git a/src/soc/rockchip/rk3288/include/soc/pmu.h b/src/soc/rockchip/rk3288/include/soc/pmu.h new file mode 100644 index 0000000..2a93515 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/pmu.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_PMU_H__ +#define __SOC_ROCKCHIP_RK3288_PMU_H__ + +#include <soc/addressmap.h> + +struct rk3288_pmu_regs { + u32 wakeup_cfg[2]; + u32 pwrdn_con; + u32 pwrdn_st; + u32 idle_req; + u32 idle_st; + u32 pwrmode_con; + u32 pwr_state; + u32 osc_cnt; + u32 pll_cnt; + u32 stabl_cnt; + u32 ddr0io_pwron_cnt; + u32 ddr1io_pwron_cnt; + u32 core_pwrdn_cnt; + u32 core_pwrup_cnt; + u32 gpu_pwrdn_cnt; + u32 gpu_pwrup_cnt; + u32 wakeup_rst_clr_cnt; + u32 sft_con; + u32 ddr_sref_st; + u32 int_con; + u32 int_st; + u32 boot_addr_sel; + u32 grf_con; + u32 gpio_sr; + u32 gpio0pull[3]; + u32 gpio0drv[3]; + u32 gpio_op; + u32 gpio0_sel18; + u32 gpio0a_iomux; + union { + u32 gpio0b_iomux; + u32 iomux_i2c0sda; + u32 iomux_tsadc_int; + }; + union { + u32 gpio0c_iomux; + u32 iomux_i2c0scl; + }; + union { + u32 gpio0d_iomux; + u32 iomux_lcdc0; + }; + u32 sys_reg[4]; +}; +check_member(rk3288_pmu_regs, sys_reg[3], 0x00a0); + +static struct rk3288_pmu_regs * const rk3288_pmu = (void *)PMU_BASE; + +#define IOMUX_I2C0SDA (1 << 14) +#define IOMUX_I2C0SCL (1 << 0) +#define IOMUX_TSADC_INT (1 << 4) + +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/pwm.h b/src/soc/rockchip/rk3288/include/soc/pwm.h new file mode 100644 index 0000000..168d8a7 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/pwm.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_PWM_H__ +#define __SOC_ROCKCHIP_RK3288_PWM_H__ + +void pwm_init(u32 id, u32 period_ns, u32 duty_ns); + +#endif + diff --git a/src/soc/rockchip/rk3288/include/soc/rk808.h b/src/soc/rockchip/rk3288/include/soc/rk808.h new file mode 100644 index 0000000..e03ace8 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/rk808.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__ +#define __SOC_ROCKCHIP_RK3288_PMIC_H__ + +void rk808_configure_switch(uint8_t bus, int sw, int enabled); +void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts); +void rk808_configure_buck(uint8_t bus, int buck, int millivolts); + +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/sdram.h b/src/soc/rockchip/rk3288/include/soc/sdram.h new file mode 100644 index 0000000..16e4f81 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/sdram.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_SDRAM_H__ +#define __SOC_ROCKCHIP_RK3288_SDRAM_H__ + +enum { + DDR3 = 3, + LPDDR3 = 6, + UNUSED = 0xFF, +}; + +struct rk3288_sdram_channel { + u8 rank; + u8 col; + u8 bk; + u8 bw; + u8 dbw; + u8 row_3_4; + u8 cs0_row; + u8 cs1_row; +}; + +struct rk3288_sdram_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; +}; +check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); + +struct rk3288_sdram_phy_timing { + u32 dtpr0; + u32 dtpr1; + u32 dtpr2; + u32 mr[4]; +}; + +struct rk3288_sdram_params { + struct rk3288_sdram_channel ch[2]; + struct rk3288_sdram_pctl_timing pctl_timing; + struct rk3288_sdram_phy_timing phy_timing; + u32 noc_timing; + u32 noc_activate; + u32 ddrconfig; + u32 ddr_freq; + u8 dramtype; + u8 num_channels; + u8 stride; + u8 odt; +}; + +void sdram_init(const struct rk3288_sdram_params *sdram_params); +u32 sdram_get_ram_code(void); +const struct rk3288_sdram_params *get_sdram_config(void); +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/soc.h b/src/soc/rockchip/rk3288/include/soc/soc.h new file mode 100644 index 0000000..00f35b2 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/soc.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_CPU_H__ +#define __SOC_ROCKCHIP_RK3288_CPU_H__ + +#include <arch/io.h> +#include <symbols.h> + +#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) +#define RK_SETBITS(set) RK_CLRSETBITS(0, set) +#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) + +#define FB_SIZE_KB 4096 +#define RAM_BASE_KB ((uintptr_t)_dram >> 10) +#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) + +static inline u32 get_fb_base_kb(void) +{ + return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; +} +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/spi.h b/src/soc/rockchip/rk3288/include/soc/spi.h new file mode 100644 index 0000000..bba38ef --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/spi.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_SPI_H__ +#define __SOC_ROCKCHIP_RK3288_SPI_H__ + +/* This driver serves as a CBFS media source. */ +#include <cbfs.h> +#include <spi-generic.h> +#include <stdint.h> + +struct rockchip_spi { + u32 ctrlr0; + u32 ctrlr1; + u32 spienr; + u32 ser; + u32 baudr; + u32 txftlr; + u32 rxftlr; + u32 txflr; + u32 rxflr; + u32 sr; + u32 ipr; + u32 imr; + u32 isr; + u32 risr; + u32 icr; + u32 dmacr; + u32 damtdlr; + u32 damrdlr; + u32 reserved[(0x400-0x48)/4]; + u32 txdr[0x100]; + u32 rxdr[0x100]; +}; +check_member(rockchip_spi, rxdr, 0x800); + + +#define SF_READ_DATA_CMD 0x3 + +/* --------Bit fields in CTRLR0--------begin */ + +#define SPI_DFS_OFFSET 0 /* Data Frame Size */ +#define SPI_DFS_MASK 0x3 +#define SPI_DFS_4BIT 0x00 +#define SPI_DFS_8BIT 0x01 +#define SPI_DFS_16BIT 0x02 +#define SPI_DFS_RESV 0x03 + +/* Control Frame Size */ +#define SPI_CFS_OFFSET 2 +#define SPI_CFS_MASK 0xF + +/* Serial Clock Phase */ +#define SPI_SCPH_OFFSET 6 +#define SPI_SCPH_MASK 0x1 + +/* Serial clock toggles in middle of first data bit */ +#define SPI_SCPH_TOGMID 0 + +/* Serial clock toggles at start of first data bit */ +#define SPI_SCPH_TOGSTA 1 + +/* Serial Clock Polarity */ +#define SPI_SCOL_OFFSET 7 +#define SPI_SCOL_MASK 0x1 + +/* Inactive state of clock serial clock is low */ +#define SPI_SCOL_LOW 0 + +/* Inactive state of clock serial clock is high */ +#define SPI_SCOL_HIGH 1 + +/* Chip Select Mode */ +#define SPI_CSM_OFFSET 8 +#define SPI_CSM_MASK 0x3 + +/* ss_n keep low after every frame data is transferred */ +#define SPI_CSM_KEEP 0x00 + +/* + * ss_n be high for half sclk_out cycles after + * every frame data is transferred + */ +#define SPI_CSM_HALF 0x01 + +/* ss_n be high for one sclk_out cycle after every frame data is transferred */ +#define SPI_CSM_ONE 0x02 +#define SPI_CSM_RESV 0x03 + +/* SSN to Sclk_out delay */ +#define SPI_SSN_DELAY_OFFSET 10 +#define SPI_SSN_DELAY_MASK 0x1 +/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */ +#define SPI_SSN_DELAY_HALF 0x00 +/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */ +#define SPI_SSN_DELAY_ONE 0x01 + +/* Serial Endian Mode */ +#define SPI_SEM_OFFSET 11 +#define SPI_SEM_MASK 0x1 +/* little endian */ +#define SPI_SEM_LITTLE 0x00 +/* big endian */ +#define SPI_SEM_BIG 0x01 + +/* First Bit Mode */ +#define SPI_FBM_OFFSET 12 +#define SPI_FBM_MASK 0x1 +/* first bit in MSB */ +#define SPI_FBM_MSB 0x00 +/* first bit in LSB */ +#define SPI_FBM_LSB 0x01 + +/* Byte and Halfword Transform */ +#define SPI_HALF_WORLD_TX_OFFSET 13 +#define SPI_HALF_WORLD_MASK 0x1 +/* apb 16bit write/read, spi 8bit write/read */ +#define SPI_APB_16BIT 0x00 +/* apb 8bit write/read, spi 8bit write/read */ +#define SPI_APB_8BIT 0x01 + +/* Rxd Sample Delay */ +#define SPI_RXDSD_OFFSET 14 +#define SPI_RXDSD_MASK 0x3 + +/* Frame Format */ +#define SPI_FRF_OFFSET 16 +#define SPI_FRF_MASK 0x3 +/* motorola spi */ +#define SPI_FRF_SPI 0x00 +/* Texas Instruments SSP*/ +#define SPI_FRF_SSP 0x01 +/* National Semiconductors Microwire */ +#define SPI_FRF_MICROWIRE 0x02 +#define SPI_FRF_RESV 0x03 + +/* Transfer Mode */ +#define SPI_TMOD_OFFSET 18 +#define SPI_TMOD_MASK 0x3 +/* xmit & recv */ +#define SPI_TMOD_TR 0x00 +/* xmit only */ +#define SPI_TMOD_TO 0x01 +/* recv only */ +#define SPI_TMOD_RO 0x02 +#define SPI_TMOD_RESV 0x03 + +/* Operation Mode */ +#define SPI_OMOD_OFFSET 20 +#define SPI_OMOD_MASK 0x1 +/* Master Mode */ +#define SPI_OMOD_MASTER 0x00 +/* Slave Mode */ +#define SPI_OMOD_SLAVE 0x01 + +/* --------Bit fields in CTRLR0--------end */ +/* Bit fields in SR, 7 bits */ +#define SR_MASK 0x7f +#define SR_BUSY (1 << 0) +#define SR_TF_FULL (1 << 1) +#define SR_TF_EMPT (1 << 2) +#define SR_RF_EMPT (1 << 3) +#define SR_RF_FULL (1 << 4) + +/* Bit fields in ISR, IMR, RISR, 7 bits */ +#define SPI_INT_TXEI (1 << 0) +#define SPI_INT_TXOI (1 << 1) +#define SPI_INT_RXUI (1 << 2) +#define SPI_INT_RXOI (1 << 3) +#define SPI_INT_RXFI (1 << 4) + +/* Bit fields in DMACR */ +#define SPI_DMACR_TX_ENABLE (1 << 1) +#define SPI_DMACR_RX_ENABLE (1 << 0) + +/* Bit fields in ICR */ +#define SPI_CLEAR_INT_ALL (1 << 0) +#define SPI_CLEAR_INT_RXUI (1 << 1) +#define SPI_CLEAR_INT_RXOI (1 << 2) +#define SPI_CLEAR_INT_TXOI (1 << 3) + +/* Serve as CBFS media source */ +int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media, + void *buffer_address, + size_t buffer_size); +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); + +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/timer.h b/src/soc/rockchip/rk3288/include/soc/timer.h new file mode 100644 index 0000000..2301686 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/timer.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__ +#define __SOC_ROCKCHIP_RK3288_TIMER_H__ + +#include <inttypes.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <timer.h> + +static const u32 clocks_per_usec = OSC_HZ/USECS_PER_SEC; + +struct rk3288_timer { + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; +}; + +static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE; + +#define TIMER_LOAD_VAL 0xffffffff + +void rk3288_init_timer(void); + +#endif /* __SOC_ROCKCHIP_RK3288_TIMER_H__ */ diff --git a/src/soc/rockchip/rk3288/include/soc/tsadc.h b/src/soc/rockchip/rk3288/include/soc/tsadc.h new file mode 100644 index 0000000..7412110 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/tsadc.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_TSADC_H__ +#define __SOC_ROCKCHIP_RK3288_TSADC_H__ + +void tsadc_init(void); + +#endif diff --git a/src/soc/rockchip/rk3288/media.c b/src/soc/rockchip/rk3288/media.c index f2471f9..7f0ea51 100644 --- a/src/soc/rockchip/rk3288/media.c +++ b/src/soc/rockchip/rk3288/media.c @@ -18,10 +18,9 @@ */
#include <cbfs.h> +#include <soc/spi.h> #include <symbols.h>
-#include "spi.h" - int init_default_cbfs_media(struct cbfs_media *media) { return initialize_rockchip_spi_cbfs_media(media, diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld deleted file mode 100644 index 2ddb6a6..0000000 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> - -#include <arch/header.ld> - -/* Note: The BootROM will jump to 0xFF704004 after loading bootblock, - * so the bootblock loading address must be at 0xFF704004. - */ -SECTIONS -{ - DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) - POSTRAM_CBFS_CACHE(0x01000000, 1M) - DMA_COHERENT(0x10000000, 2M) - - SRAM_START(0xFF700000) - TTB(0xFF700000, 16K) - BOOTBLOCK(0xFF704004, 15K - 4) - TTB_SUBTABLES(0xFF707c00, 1K) - VBOOT2_WORK(0xFF708000, 16K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K) - PRERAM_CBFS_CACHE(0xFF716000, 4K) - STACK(0xFF717000, 4K) - SRAM_END(0xFF718000) - - /* 4K of special SRAM in PMU power domain. Careful: only supports 32-bit - * wide write accesses! Only use with MMU and writeback mapping. */ - SYMBOL(pmu_sram, 0xFF720000) - SYMBOL(epmu_sram, 0xFF721000) -} diff --git a/src/soc/rockchip/rk3288/monotonic_timer.c b/src/soc/rockchip/rk3288/monotonic_timer.c index d33ed68..4062860 100644 --- a/src/soc/rockchip/rk3288/monotonic_timer.c +++ b/src/soc/rockchip/rk3288/monotonic_timer.c @@ -17,11 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/timer.h> #include <stdint.h> #include <timer.h> -#include <arch/io.h> -#include "addressmap.h" -#include "timer.h"
static uint64_t timer_raw_value(void) { diff --git a/src/soc/rockchip/rk3288/pmu.h b/src/soc/rockchip/rk3288/pmu.h deleted file mode 100644 index 23ca8b1..0000000 --- a/src/soc/rockchip/rk3288/pmu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_PMU_H__ -#define __SOC_ROCKCHIP_RK3288_PMU_H__ -#include "addressmap.h" - -struct rk3288_pmu_regs { - u32 wakeup_cfg[2]; - u32 pwrdn_con; - u32 pwrdn_st; - u32 idle_req; - u32 idle_st; - u32 pwrmode_con; - u32 pwr_state; - u32 osc_cnt; - u32 pll_cnt; - u32 stabl_cnt; - u32 ddr0io_pwron_cnt; - u32 ddr1io_pwron_cnt; - u32 core_pwrdn_cnt; - u32 core_pwrup_cnt; - u32 gpu_pwrdn_cnt; - u32 gpu_pwrup_cnt; - u32 wakeup_rst_clr_cnt; - u32 sft_con; - u32 ddr_sref_st; - u32 int_con; - u32 int_st; - u32 boot_addr_sel; - u32 grf_con; - u32 gpio_sr; - u32 gpio0pull[3]; - u32 gpio0drv[3]; - u32 gpio_op; - u32 gpio0_sel18; - u32 gpio0a_iomux; - union { - u32 gpio0b_iomux; - u32 iomux_i2c0sda; - u32 iomux_tsadc_int; - }; - union { - u32 gpio0c_iomux; - u32 iomux_i2c0scl; - }; - union { - u32 gpio0d_iomux; - u32 iomux_lcdc0; - }; - u32 sys_reg[4]; -}; -check_member(rk3288_pmu_regs, sys_reg[3], 0x00a0); - -static struct rk3288_pmu_regs * const rk3288_pmu = (void *)PMU_BASE; - -#define IOMUX_I2C0SDA (1 << 14) -#define IOMUX_I2C0SCL (1 << 0) -#define IOMUX_TSADC_INT (1 << 4) - -#endif diff --git a/src/soc/rockchip/rk3288/pwm.c b/src/soc/rockchip/rk3288/pwm.c index 7f659f2..a447249 100644 --- a/src/soc/rockchip/rk3288/pwm.c +++ b/src/soc/rockchip/rk3288/pwm.c @@ -17,18 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <console/console.h> #include <arch/io.h> -#include <stdlib.h> #include <assert.h> -#include <timer.h> +#include <console/console.h> #include <delay.h> - -#include "addressmap.h" -#include "grf.h" -#include "soc.h" -#include "pwm.h" -#include "clock.h" +#include <soc/addressmap.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/pwm.h> +#include <soc/clock.h> +#include <stdlib.h> +#include <timer.h>
struct pwm_ctl { u32 pwm_cnt; diff --git a/src/soc/rockchip/rk3288/pwm.h b/src/soc/rockchip/rk3288/pwm.h deleted file mode 100644 index 168d8a7..0000000 --- a/src/soc/rockchip/rk3288/pwm.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_PWM_H__ -#define __SOC_ROCKCHIP_RK3288_PWM_H__ - -void pwm_init(u32 id, u32 period_ns, u32 duty_ns); - -#endif - diff --git a/src/soc/rockchip/rk3288/rk808.c b/src/soc/rockchip/rk3288/rk808.c index 48cfa86..aa39b8d 100644 --- a/src/soc/rockchip/rk3288/rk808.c +++ b/src/soc/rockchip/rk3288/rk808.c @@ -19,11 +19,11 @@
#include <assert.h> #include <console/console.h> +#include <delay.h> #include <device/i2c.h> +#include <soc/rk808.h> #include <stdint.h> #include <stdlib.h> -#include <delay.h> -#include "rk808.h"
#define RK808_ADDR 0x1b
diff --git a/src/soc/rockchip/rk3288/rk808.h b/src/soc/rockchip/rk3288/rk808.h deleted file mode 100644 index e03ace8..0000000 --- a/src/soc/rockchip/rk3288/rk808.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__ -#define __SOC_ROCKCHIP_RK3288_PMIC_H__ - -void rk808_configure_switch(uint8_t bus, int sw, int enabled); -void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts); -void rk808_configure_buck(uint8_t bus, int buck, int millivolts); - -#endif diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 2b0a396..d49b860 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -17,16 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <arch/io.h> -#include <string.h> -#include <types.h> #include <console/console.h> #include <delay.h> -#include "addressmap.h" -#include "clock.h" -#include "sdram.h" -#include "grf.h" -#include "soc.h" -#include "pmu.h" +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/sdram.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/pmu.h> +#include <string.h> +#include <types.h>
struct rk3288_ddr_pctl_regs { u32 scfg; diff --git a/src/soc/rockchip/rk3288/sdram.h b/src/soc/rockchip/rk3288/sdram.h deleted file mode 100644 index 1da14b7..0000000 --- a/src/soc/rockchip/rk3288/sdram.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_SDRAM_H__ -#define __SOC_ROCKCHIP_RK3288_SDRAM_H__ - -#include <arch/io.h> - -enum { - DDR3 = 3, - LPDDR3 = 6, - UNUSED = 0xFF, -}; - -struct rk3288_sdram_channel { - u8 rank; - u8 col; - u8 bk; - u8 bw; - u8 dbw; - u8 row_3_4; - u8 cs0_row; - u8 cs1_row; -}; - -struct rk3288_sdram_pctl_timing { - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 tdpd; -}; -check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); - -struct rk3288_sdram_phy_timing { - u32 dtpr0; - u32 dtpr1; - u32 dtpr2; - u32 mr[4]; -}; - -struct rk3288_sdram_params { - struct rk3288_sdram_channel ch[2]; - struct rk3288_sdram_pctl_timing pctl_timing; - struct rk3288_sdram_phy_timing phy_timing; - u32 noc_timing; - u32 noc_activate; - u32 ddrconfig; - u32 ddr_freq; - u8 dramtype; - u8 num_channels; - u8 stride; - u8 odt; -}; - -void sdram_init(const struct rk3288_sdram_params *sdram_params); -u32 sdram_get_ram_code(void); -const struct rk3288_sdram_params *get_sdram_config(void); -#endif diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 0985c08..f5e52eb 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -17,16 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <stdlib.h> -#include <string.h> -#include <stddef.h> -#include <delay.h> +#include <arch/cache.h> +#include <cbmem.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> -#include <cbmem.h> -#include <arch/cache.h> -#include <soc/rockchip/rk3288/gpio.h> -#include "soc.h" +#include <soc/gpio.h> +#include <soc/soc.h> +#include <stddef.h> +#include <stdlib.h> +#include <string.h> + #include "chip.h"
static void soc_enable(device_t dev) diff --git a/src/soc/rockchip/rk3288/soc.h b/src/soc/rockchip/rk3288/soc.h deleted file mode 100644 index 00f35b2..0000000 --- a/src/soc/rockchip/rk3288/soc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_CPU_H__ -#define __SOC_ROCKCHIP_RK3288_CPU_H__ - -#include <arch/io.h> -#include <symbols.h> - -#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) -#define RK_SETBITS(set) RK_CLRSETBITS(0, set) -#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) - -#define FB_SIZE_KB 4096 -#define RAM_BASE_KB ((uintptr_t)_dram >> 10) -#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) - -static inline u32 get_fb_base_kb(void) -{ - return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; -} -#endif diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 796107e..6ece8c1 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -17,18 +17,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <console/console.h> #include <arch/io.h> -#include <stdlib.h> #include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <endian.h> +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/clock.h> #include <spi-generic.h> #include <spi_flash.h> -#include <delay.h> +#include <stdlib.h> #include <timer.h> -#include <endian.h> -#include "addressmap.h" -#include "spi.h" -#include "clock.h"
struct rockchip_spi_slave { struct spi_slave slave; diff --git a/src/soc/rockchip/rk3288/spi.h b/src/soc/rockchip/rk3288/spi.h deleted file mode 100644 index bba38ef..0000000 --- a/src/soc/rockchip/rk3288/spi.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_SPI_H__ -#define __SOC_ROCKCHIP_RK3288_SPI_H__ - -/* This driver serves as a CBFS media source. */ -#include <cbfs.h> -#include <spi-generic.h> -#include <stdint.h> - -struct rockchip_spi { - u32 ctrlr0; - u32 ctrlr1; - u32 spienr; - u32 ser; - u32 baudr; - u32 txftlr; - u32 rxftlr; - u32 txflr; - u32 rxflr; - u32 sr; - u32 ipr; - u32 imr; - u32 isr; - u32 risr; - u32 icr; - u32 dmacr; - u32 damtdlr; - u32 damrdlr; - u32 reserved[(0x400-0x48)/4]; - u32 txdr[0x100]; - u32 rxdr[0x100]; -}; -check_member(rockchip_spi, rxdr, 0x800); - - -#define SF_READ_DATA_CMD 0x3 - -/* --------Bit fields in CTRLR0--------begin */ - -#define SPI_DFS_OFFSET 0 /* Data Frame Size */ -#define SPI_DFS_MASK 0x3 -#define SPI_DFS_4BIT 0x00 -#define SPI_DFS_8BIT 0x01 -#define SPI_DFS_16BIT 0x02 -#define SPI_DFS_RESV 0x03 - -/* Control Frame Size */ -#define SPI_CFS_OFFSET 2 -#define SPI_CFS_MASK 0xF - -/* Serial Clock Phase */ -#define SPI_SCPH_OFFSET 6 -#define SPI_SCPH_MASK 0x1 - -/* Serial clock toggles in middle of first data bit */ -#define SPI_SCPH_TOGMID 0 - -/* Serial clock toggles at start of first data bit */ -#define SPI_SCPH_TOGSTA 1 - -/* Serial Clock Polarity */ -#define SPI_SCOL_OFFSET 7 -#define SPI_SCOL_MASK 0x1 - -/* Inactive state of clock serial clock is low */ -#define SPI_SCOL_LOW 0 - -/* Inactive state of clock serial clock is high */ -#define SPI_SCOL_HIGH 1 - -/* Chip Select Mode */ -#define SPI_CSM_OFFSET 8 -#define SPI_CSM_MASK 0x3 - -/* ss_n keep low after every frame data is transferred */ -#define SPI_CSM_KEEP 0x00 - -/* - * ss_n be high for half sclk_out cycles after - * every frame data is transferred - */ -#define SPI_CSM_HALF 0x01 - -/* ss_n be high for one sclk_out cycle after every frame data is transferred */ -#define SPI_CSM_ONE 0x02 -#define SPI_CSM_RESV 0x03 - -/* SSN to Sclk_out delay */ -#define SPI_SSN_DELAY_OFFSET 10 -#define SPI_SSN_DELAY_MASK 0x1 -/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */ -#define SPI_SSN_DELAY_HALF 0x00 -/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */ -#define SPI_SSN_DELAY_ONE 0x01 - -/* Serial Endian Mode */ -#define SPI_SEM_OFFSET 11 -#define SPI_SEM_MASK 0x1 -/* little endian */ -#define SPI_SEM_LITTLE 0x00 -/* big endian */ -#define SPI_SEM_BIG 0x01 - -/* First Bit Mode */ -#define SPI_FBM_OFFSET 12 -#define SPI_FBM_MASK 0x1 -/* first bit in MSB */ -#define SPI_FBM_MSB 0x00 -/* first bit in LSB */ -#define SPI_FBM_LSB 0x01 - -/* Byte and Halfword Transform */ -#define SPI_HALF_WORLD_TX_OFFSET 13 -#define SPI_HALF_WORLD_MASK 0x1 -/* apb 16bit write/read, spi 8bit write/read */ -#define SPI_APB_16BIT 0x00 -/* apb 8bit write/read, spi 8bit write/read */ -#define SPI_APB_8BIT 0x01 - -/* Rxd Sample Delay */ -#define SPI_RXDSD_OFFSET 14 -#define SPI_RXDSD_MASK 0x3 - -/* Frame Format */ -#define SPI_FRF_OFFSET 16 -#define SPI_FRF_MASK 0x3 -/* motorola spi */ -#define SPI_FRF_SPI 0x00 -/* Texas Instruments SSP*/ -#define SPI_FRF_SSP 0x01 -/* National Semiconductors Microwire */ -#define SPI_FRF_MICROWIRE 0x02 -#define SPI_FRF_RESV 0x03 - -/* Transfer Mode */ -#define SPI_TMOD_OFFSET 18 -#define SPI_TMOD_MASK 0x3 -/* xmit & recv */ -#define SPI_TMOD_TR 0x00 -/* xmit only */ -#define SPI_TMOD_TO 0x01 -/* recv only */ -#define SPI_TMOD_RO 0x02 -#define SPI_TMOD_RESV 0x03 - -/* Operation Mode */ -#define SPI_OMOD_OFFSET 20 -#define SPI_OMOD_MASK 0x1 -/* Master Mode */ -#define SPI_OMOD_MASTER 0x00 -/* Slave Mode */ -#define SPI_OMOD_SLAVE 0x01 - -/* --------Bit fields in CTRLR0--------end */ -/* Bit fields in SR, 7 bits */ -#define SR_MASK 0x7f -#define SR_BUSY (1 << 0) -#define SR_TF_FULL (1 << 1) -#define SR_TF_EMPT (1 << 2) -#define SR_RF_EMPT (1 << 3) -#define SR_RF_FULL (1 << 4) - -/* Bit fields in ISR, IMR, RISR, 7 bits */ -#define SPI_INT_TXEI (1 << 0) -#define SPI_INT_TXOI (1 << 1) -#define SPI_INT_RXUI (1 << 2) -#define SPI_INT_RXOI (1 << 3) -#define SPI_INT_RXFI (1 << 4) - -/* Bit fields in DMACR */ -#define SPI_DMACR_TX_ENABLE (1 << 1) -#define SPI_DMACR_RX_ENABLE (1 << 0) - -/* Bit fields in ICR */ -#define SPI_CLEAR_INT_ALL (1 << 0) -#define SPI_CLEAR_INT_RXUI (1 << 1) -#define SPI_CLEAR_INT_RXOI (1 << 2) -#define SPI_CLEAR_INT_TXOI (1 << 3) - -/* Serve as CBFS media source */ -int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size); -void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); - -#endif diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index 91186cc..7162482 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <arch/io.h> #include <console/console.h> #include <delay.h> -#include <arch/io.h> -#include "timer.h" +#include <soc/timer.h> +#include <timer.h>
void init_timer(void) { diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h deleted file mode 100644 index 8507939..0000000 --- a/src/soc/rockchip/rk3288/timer.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__ -#define __SOC_ROCKCHIP_RK3288_TIMER_H__ - -#include <inttypes.h> -#include <timer.h> -#include "addressmap.h" -#include "clock.h" - -static const u32 clocks_per_usec = OSC_HZ/USECS_PER_SEC; - -struct rk3288_timer { - u32 timer_load_count0; - u32 timer_load_count1; - u32 timer_curr_value0; - u32 timer_curr_value1; - u32 timer_ctrl_reg; - u32 timer_int_status; -}; - -static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE; - -#define TIMER_LOAD_VAL 0xffffffff - -void rk3288_init_timer(void); - -#endif /* __SOC_ROCKCHIP_RK3288_TIMER_H__ */ diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 73980a0..b7d8e9d 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -17,16 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <arch/io.h> #include <assert.h> #include <console/console.h> +#include <delay.h> +#include <soc/clock.h> +#include <soc/grf.h> +#include <soc/pmu.h> +#include <soc/tsadc.h> #include <stdint.h> #include <stdlib.h> -#include <arch/io.h> -#include <delay.h> -#include "tsadc.h" -#include "clock.h" -#include "pmu.h" -#include "grf.h"
struct rk3288_tsadc_regs { u32 user_con; diff --git a/src/soc/rockchip/rk3288/tsadc.h b/src/soc/rockchip/rk3288/tsadc.h deleted file mode 100644 index 7412110..0000000 --- a/src/soc/rockchip/rk3288/tsadc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_TSADC_H__ -#define __SOC_ROCKCHIP_RK3288_TSADC_H__ - -void tsadc_init(void); - -#endif diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c index 60b14a3..01759fe 100644 --- a/src/soc/rockchip/rk3288/uart.c +++ b/src/soc/rockchip/rk3288/uart.c @@ -17,12 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> #include <console/console.h> /* for __console definition */ -#include <stdint.h> +#include <console/uart.h> #include <drivers/uart/uart8250reg.h> +#include <stdint.h>
/* * TODO: Use DRIVERS_UART_8250MEM driver instead.