Gabe Black (gabeblack@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3067
-gerrit
commit d6413a8a7ca52d9830d18152957175d39a7e2518 Author: Gabe Black gabeblack@chromium.org Date: Wed Apr 10 14:34:57 2013 -0700
Snow: Set up the ChromeOS GPIOs as inputs during the ROM stage.
We need these to be inputs so they can be read when populating the coreboot tables. It seems like a good idea to do this early to ensure that the input gate capacitance has had a chance to charge, and if we decide to use actually use that information during the ROM stage to do earlier RW firmware selection.
It is not guarded by a ChromeOS config variable because those lines are always intended to be input GPIOs, regardless of whether we're running ChromeOS or not.
Change-Id: Id76008931b5081253737c6676980a1bdb476ac09 Signed-off-by: Gabe Black gabeblack@chromium.org --- src/mainboard/google/snow/romstage.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index d34c379..7a26ed9 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -27,6 +27,7 @@ #include <arch/gpio.h> #include <cpu/samsung/exynos5-common/i2c.h> #include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/gpio.h> #include <cpu/samsung/exynos5250/setup.h> @@ -118,6 +119,31 @@ static void graphics(void) exynos_pinmux_config(PERIPH_ID_DPHPD, 0); }
+static void chromeos_gpios(void) +{ + struct exynos5_gpio_part1 *gpio_pt1; + struct exynos5_gpio_part2 *gpio_pt2; + + enum { + WP_GPIO = 6, + FORCE_RECOVERY_MODE = 0, + LID_OPEN = 5 + }; + + gpio_pt1 = (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE; + gpio_pt2 = (struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE; + + s5p_gpio_direction_input(&gpio_pt1->d1, WP_GPIO); + s5p_gpio_set_pull(&gpio_pt1->d1, WP_GPIO, EXYNOS_GPIO_PULL_NONE); + + s5p_gpio_direction_input(&gpio_pt1->y1, FORCE_RECOVERY_MODE); + s5p_gpio_set_pull(&gpio_pt1->y1, FORCE_RECOVERY_MODE, + EXYNOS_GPIO_PULL_NONE); + + s5p_gpio_direction_input(&gpio_pt2->x3, LID_OPEN); + s5p_gpio_set_pull(&gpio_pt2->x3, LID_OPEN, EXYNOS_GPIO_PULL_NONE); +} + void main(void) { struct mem_timings *mem; @@ -161,6 +187,8 @@ void main(void)
initialize_s5p_mshc();
+ chromeos_gpios(); + graphics();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");