[coreboot-gerrit] Change in coreboot[master]: mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44530 )

Change subject: mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3
......................................................................

mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3

There are only headers for the SoC's UART 0 and 1 on the board.

BUG=b:165020060
TEST=Linux only detects UART 0 and 1.

Change-Id: I45929f65a5f844ae5cef792b11176f487c80766f
Signed-off-by: Felix Held 
---
M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44530/1

diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
index ffc18a0..0004ecd 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
+++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
@@ -155,4 +155,10 @@
    	device pci 18.6 on  end
    	device pci 18.7 on  end
    end # domain
+
+	device mmio 0xfedc9000 on  end # UART0
+	device mmio 0xfedca000 on  end # UART1
+	device mmio 0xfedce000 off end # UART2
+	device mmio 0xfedcf000 off end # UART3
+
 end	# chip soc/amd/picasso