Attention is currently required from: Patrick Rudolph. Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59484 )
Change subject: soc/intel/elkhartlake: Disable Intel PSE by default ......................................................................
soc/intel/elkhartlake: Disable Intel PSE by default
Disable PSE loading by default. If left enabled (current default), the EHL coreboot will end up in endless restart loop, due to FSP unable to locate PSE FW image and trigger global reset.
However disabling this flag (PchPseEnable) will cause the coreboot to trigger a single reset due to CSE signal (HECI: CSE does not meet required prerequisites). The reason behind this is that FSP need to perform static disabling (power gate) to fully shut down PSE HW, and to do this will need to global reset entire system including CSE. Then PMC will power gate PSE from the start.
To avoid this behavior, the best way to disable PSE is to disable via IFWI FIT softstrap (For specific detail can refer to Intel PSE documentation). With this, PMC will power gate PSE from the first cold boot and system will boot happily without sigle reset behavior.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f --- M src/soc/intel/elkhartlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/59484/1
diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index a15b030..ecb6304 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -123,6 +123,8 @@ config->ibecc.region_mask); } } + /* PSE (Intel Programmable Services Engine) switch */ + m_cfg->PchPseEnable = 0; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)