Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59931 )
Change subject: soc/amd/common/block/include/spi: update fch_spi_early_init description ......................................................................
soc/amd/common/block/include/spi: update fch_spi_early_init description
commit 90ac882a32075b44435aa19ea664b89b79cac76e (soc/amd/common/block/ spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST) introduced a Kconfig option to enable/disable the 4DW burst support in the SPI flash data prefetcher, but missed to update the documentation above the fch_spi_early_init prototype, so update the outdated documentation now.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b --- M src/soc/amd/common/block/include/amdblocks/spi.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/59931/1
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 81da5dd..5c3bd0e 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -94,7 +94,7 @@ * Perform early SPI initialization: * 1. Sets SPI ROM base and enables SPI ROM * 2. Enables SPI ROM prefetching - * 3. Disables 4dw burst + * 3. Disables 4 DWORD burst if !SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST * 4. Configures SPI speed and read mode. * * This function expects SoC to include soc_amd_common_config in chip SoC config and uses