Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84080?usp=email )
Change subject: soc/intel/adl: Prevent unconditional legacy COM ports initialization ......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84080/comment/cfa9060f_f33aea30?usp... : PS1, Line 14: These COM ports are being activated unconditionally, which is : undesirable for the Intel Alder Lake platform and causes traffic over : the IO bus.
I don't understand this. What code is generating those writes?
sorry if things are not cleared. As we are not using Legacy UART for ChromeOS device but looking at the Alder Lake code, we found that Legacy COMs are default enabled and we have observed some activity across those ports. Hence, pushed this CL to ensure legacy COMs are not getting enabled when the desired kconfig are not being selected
After booting to Kernel, we are seeing some traffic. For sure that is not any FW code.
marking the comment resolved and feel free opening if not statisfied.
https://review.coreboot.org/c/coreboot/+/84080/comment/1d26dff9_d89dcc3e/ CL enabled (soc/alderlake: Enable all bits for IO decode / enable register) all LPC decode range looks like. I'm not sure if someone really wise to use parallel ports for printer even using Alder Lake chipset ?
Adding @Sean Rhodes