Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44724
to review the following change.
Change subject: soc/mediatek/mt8192: Do dramc runtime config settings ......................................................................
soc/mediatek/mt8192: Do dramc runtime config settings
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Id7ccf0e2332f789f5ae50ec80479c4cd48bb9b40 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_tracking.c 3 files changed, 821 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44724/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index f42ae75..bfa3316 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,7 +16,7 @@ verstage-y += ../common/uart.c
romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 11c5d3a..c3c19bf 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -297,7 +297,12 @@ } dqsosc_shu_settings(cali, dqsosc_thrd_inc, dqsosc_thrd_dec); dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); + dramc_dqs_precalculation_preset(cali); dramc_dual_rank_rx_datlat_cal(cali); + + if (cali->support_ranks == DUAL_RANK_DDR) + xrtwtw_shu_setting(cali); + }
static void dramc_calibration_all_channels(struct ddr_cali *cali) @@ -431,4 +436,6 @@ first_freq_k = false; dramc_info("frequency %d calibration finish\n", get_frequency(&cali)); } + + dramc_runtime_config(&cali); } diff --git a/src/soc/mediatek/mt8192/dramc_tracking.c b/src/soc/mediatek/mt8192/dramc_tracking.c new file mode 100644 index 0000000..3c13447 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_tracking.c @@ -0,0 +1,813 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +static void dramc_dqs_precalculation_enable(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_pre_tdqsck1, + MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_pre_tdqsck1, + MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_pre_tdqsck1, + MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 0x1); + } +} + +static void dramc_hw_gating_debug(bool enable) +{ + u8 dbg_en = enable ? 0x3 : 0x0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_DBG_EN, dbg_en, + MISC_STBCAL2_STB_PIDLYCG_IG, enable, + MISC_STBCAL2_STB_UIDLYCG_IG, enable, + MISC_STBCAL2_STB_GERRSTOP, enable, + MISC_STBCAL2_STB_DBG_CG_AO, 0, + MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 1); + } +} + +static void tx_picg_new_mode_enable(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl3, + MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0, + MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0, + MISC_CTRL3_ARPI_CG_DQS_OPT, 0, + MISC_CTRL3_ARPI_CG_DQ_OPT, 0); + } +} + +static void enable_common_dcm_non_shuffle(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, + ACTIMING_CTRL_SEQCLKRUN3, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0, + MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0, + MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1, + MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17, + MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0, + MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3, + MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1, + MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0, + MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi1, + CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dummy_rd, + DUMMY_RD_DUMMY_RD_PA_OPT, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl3, + MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0, + MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0, + MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0, + MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0, + MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0, + MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0, + MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0, + MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0, + MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0, + MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0); + } +} + +static void enable_common_dcm_shuffle(u8 shuffle) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd13 + shuffle * SHU_OFFSET, + SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl + shuffle * SHU_OFFSET, + MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 0x1, + MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8 + shuffle * SHU_OFFSET, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1); + write32(&ch[chn].phy_ao.misc_shu_cg_ctrl0 + shuffle * SHU_OFFSET, + 0x33403000); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8 + shuffle * SHU_OFFSET, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq7 + shuffle * SHU_OFFSET, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd7 + shuffle * SHU_OFFSET, + SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0, + SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq7 + shuffle * SHU_OFFSET, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0); + } +} + +void enable_phy_dcm_shuffle(dcm_state enable, u8 shuffle) +{ + u8 val = enable ? 0 : 1; + enable_common_dcm_shuffle(shuffle); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8 + shuffle * SHU_OFFSET, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, val); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd8 + shuffle * SHU_OFFSET, + SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, val, + SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, val, + SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, val); + SET32_BITFIELDS(&ch[chn].ao.shu_aphy_tx_picg_ctrl + shuffle * SHU_OFFSET, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, enable); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8 + shuffle * SHU_OFFSET, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, val, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, val); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_odtctrl + shuffle * SHU_OFFSET, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, val); + } +} + +void enable_phy_dcm_non_shuffle(dcm_state enable) +{ + enable_common_dcm_non_shuffle(); + + if (enable) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.tx_cg_set0, + TX_CG_SET0_DWCLKRUN, 0x0, + TX_CG_SET0_SELPH_CG_DIS, 0x0, + TX_CG_SET0_SELPH_4LCG_DIS, 0x0, + TX_CG_SET0_TX_ATK_CLKRUN, 0x0, + TX_CG_SET0_WDATA_CG_DIS, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl5, + MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x1, + MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x1, + MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x1, + MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x1, + MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x1, + MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x0, + MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0); + SET32_BITFIELDS(&ch[chn].ao.misctl0, + MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x0); + SET32_BITFIELDS(&ch[chn].ao.sref_dpd_ctrl, + SREF_DPD_CTRL_SREF_CG_OPT, 0x0); + SET32_BITFIELDS(&ch[chn].ao.rx_cg_set0, + RX_CG_SET0_RDYCKAR, 0x0, + RX_CG_SET0_RDATCKAR, 0x0); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, + ACTIMING_CTRL_SEQCLKRUN2, 0x0, + ACTIMING_CTRL_SEQCLKRUN, 0x0); + SET32_BITFIELDS(&ch[chn].ao.scsmctrl_cg, + SCSMCTRL_CG_SCARB_SM_CGAR, 0x0, + SCSMCTRL_CG_SCSM_CGAR, 0x0); + SET32_BITFIELDS(&ch[chn].ao.cmd_dec_ctrl0, + CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x0); + SET32_BITFIELDS(&ch[chn].ao.clkar, + CLKAR_REQQUE_PACG_DIS, 0x0, + CLKAR_REQQUECLKRUN, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x0); + SET32_BITFIELDS(&ch[chn].ao.ddrcommon0, + DDRCOMMON0_DISSTOP26M, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_DVFS_CG_OPT, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dcm_ctrl0, DCM_CTRL0_BCLKAR, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x1, + DRAMC_PD_CTRL_DCMEN2, 0x1, + DRAMC_PD_CTRL_DCMEN, 0x1, + DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x0, + DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x0, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x0, + DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x0, + DRAMC_PD_CTRL_DCMENNOTRFC, 0x1, + DRAMC_PD_CTRL_COMBCLKCTRL, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl3, + MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x0, + MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl4, + MISC_CTRL4_R_OPT2_CG_MCK, 0x1, + MISC_CTRL4_R_OPT2_MPDIV_CG, 0x1, + MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x1, + MISC_CTRL4_R_OPT2_CG_DQ, 0x1, + MISC_CTRL4_R_OPT2_CG_DQS, 0x1, + MISC_CTRL4_R_OPT2_CG_DQM, 0x1, + MISC_CTRL4_R_OPT2_CG_CMD, 0x1, + MISC_CTRL4_R_OPT2_CG_CLK, 0x1, + MISC_CTRL4_R_OPT2_CG_CS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.tx_tracking_set0, + TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x0, + TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x0, + TX_TRACKING_SET0_HMRRSEL_CGAR, 0x0); + SET32_BITFIELDS(&ch[chn].ao.zq_set0, + ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x0, + ZQ_SET0_ZQMASK_CGAR, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_autok_cfg0, + MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x0); + } + } else { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.tx_cg_set0, + TX_CG_SET0_DWCLKRUN, 0x1, + TX_CG_SET0_SELPH_CG_DIS, 0x1, + TX_CG_SET0_SELPH_4LCG_DIS, 0x1, + TX_CG_SET0_TX_ATK_CLKRUN, 0x1, + TX_CG_SET0_WDATA_CG_DIS, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl5, + MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x0, + MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x0, + MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x0, + MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x0, + MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x0, + MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x1, + MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x1, + MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0); + SET32_BITFIELDS(&ch[chn].ao.misctl0, + MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.sref_dpd_ctrl, + SREF_DPD_CTRL_SREF_CG_OPT, 0x1); + SET32_BITFIELDS(&ch[chn].ao.rx_cg_set0, + RX_CG_SET0_RDYCKAR, 0x1, + RX_CG_SET0_RDATCKAR, 0x1); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, + ACTIMING_CTRL_SEQCLKRUN2, 0x1, + ACTIMING_CTRL_SEQCLKRUN, 0x1); + SET32_BITFIELDS(&ch[chn].ao.scsmctrl_cg, + SCSMCTRL_CG_SCARB_SM_CGAR, 0x1, + SCSMCTRL_CG_SCSM_CGAR, 0x1); + SET32_BITFIELDS(&ch[chn].ao.cmd_dec_ctrl0, + CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.clkar, + CLKAR_REQQUE_PACG_DIS, 0x7fff, + CLKAR_REQQUECLKRUN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x1); + SET32_BITFIELDS(&ch[chn].ao.ddrcommon0, + DDRCOMMON0_DISSTOP26M, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_DVFS_CG_OPT, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dcm_ctrl0, DCM_CTRL0_BCLKAR, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x0, + DRAMC_PD_CTRL_DCMEN2, 0x0, + DRAMC_PD_CTRL_DCMEN, 0x0, + DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x1, + DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x1, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x1, + DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x1, + DRAMC_PD_CTRL_DCMENNOTRFC, 0x0, + DRAMC_PD_CTRL_COMBCLKCTRL, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl3, + MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x1, + MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl4, + MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x0, + MISC_CTRL4_R_OPT2_CG_CLK, 0x0, + MISC_CTRL4_R_OPT2_MPDIV_CG, 0x0, + MISC_CTRL4_R_OPT2_CG_DQM, 0x0, + MISC_CTRL4_R_OPT2_CG_CMD, 0x0, + MISC_CTRL4_R_OPT2_CG_DQS, 0x0, + MISC_CTRL4_R_OPT2_CG_MCK, 0x0, + MISC_CTRL4_R_OPT2_CG_CS, 0x0, + MISC_CTRL4_R_OPT2_CG_DQ, 0x0); + SET32_BITFIELDS(&ch[chn].ao.tx_tracking_set0, + TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x1, + TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x1, + TX_TRACKING_SET0_HMRRSEL_CGAR, 0x1); + SET32_BITFIELDS(&ch[chn].ao.zq_set0, + ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x1, + ZQ_SET0_ZQMASK_CGAR, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_autok_cfg0, + MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x1); + } + } +} + +static void enable_tx_tracking(dram_freq_grp freq_group, u8 shuffle) +{ + u8 dqsosc_en = (freq_group <= DDRFREQ_400) ? 1 : 0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.shu_dqsosc_set0 + shuffle * SHU_OFFSET, + SHU_DQSOSC_SET0_DQSOSCENDIS, dqsosc_en); +} + +static void enable_gating_tracking(dram_freq_grp freq_group, u8 shuffle) +{ + u8 stbcal = (freq_group <= DDRFREQ_400) ? 0 : 1; + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal + shuffle * SHU_OFFSET, + MISC_SHU_STBCAL_STBCALEN, stbcal, + MISC_SHU_STBCAL_STB_SELPHCALEN, stbcal); +} + +static void enable_rx_dcm_dphy(dram_freq_grp freq_group, u8 shuffle) +{ + u8 precal_cg_en = (freq_group <= DDRFREQ_400) ? 1 : 0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl + shuffle * SHU_OFFSET, + MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0x1, + MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0x1, + MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT, 0x1, + MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN, 0x0, + MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN, 0x1, + MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 0x1, + MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 0x1, + MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, precal_cg_en, + MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 0x2, + MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0x0); +} + + +static void enable_clk_tx_rx_latch_en(u8 shuffle) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq13 + shuffle * SHU_OFFSET, + SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq13 + shuffle * SHU_OFFSET, + SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10 + shuffle * SHU_OFFSET, + SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10 + shuffle * SHU_OFFSET, + SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2 + shuffle * SHU_OFFSET, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2 + shuffle * SHU_OFFSET, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq11 + shuffle * SHU_OFFSET, + SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq11 + shuffle * SHU_OFFSET, + SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd11 + shuffle * SHU_OFFSET, + SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd10 + shuffle * SHU_OFFSET, + SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA, 1); + } + +} + +static void enable_tx_wdqs(u8 shuffle) +{ + u8 dqsb_read_base = 1; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq13 + shuffle * SHU_OFFSET, + SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 1, + SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, dqsb_read_base, + SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 1, + SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, + dqsb_read_base); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq13 + shuffle * SHU_OFFSET, + SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 1, + SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, dqsb_read_base, + SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 1, + SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, + dqsb_read_base); + } +} + +static void set_mr13_vrcg_to_normal_operation_shuffle(u8 shuffle) +{ + u32 value = READ32_BITFIELD(&ch[0].ao.shu_hwset_vrcg + shuffle * SHU_OFFSET, + SHU_HWSET_VRCG_HWSET_VRCG_OP); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg + shuffle * SHU_OFFSET, + SHU_HWSET_VRCG_HWSET_VRCG_OP, value & ~ BIT(3)); +} + +static void dramc_shu_tracking_dcm_en_by_sram(const struct ddr_cali* cali) +{ + u8 shuffle, chn, shuffle_save; + dram_freq_grp freq_group = 0; + dram_freq_grp freq_group_bak = get_freq_group(cali); + + struct reg_bak regs_bak[] = { + {&ch[0].phy_ao.misc_sram_dma0}, + {&ch[1].phy_ao.misc_sram_dma0}, + {&ch[0].phy_ao.misc_sram_dma1}, + {&ch[1].phy_ao.misc_sram_dma1}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + for (chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma1, + MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS, 0x1); + } + + for (shuffle = DRAM_DFS_SHU0; shuffle <= DRAM_DFS_SHU_MAX; shuffle++) { + if (shuffle < DRAM_DFS_SHU_MAX) { + /* save to shuffle */ + freq_group = get_freq_group_by_shu_save(shuffle); + for (chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma1, + MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL, shuffle); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0x1); + } + shuffle_save = DRAM_DFS_SHU1; + } else { + /* restore to SRAM */ + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + shuffle_save = DRAM_DFS_SHU0; + freq_group = freq_group_bak; + } + + enable_tx_tracking(freq_group, shuffle_save); + enable_gating_tracking(freq_group, shuffle_save); + enable_rx_dcm_dphy(freq_group, shuffle_save); + enable_clk_tx_rx_latch_en(shuffle_save); + enable_tx_wdqs(shuffle_save); + enable_phy_dcm_shuffle(DCM_ON, shuffle_save); + set_mr13_vrcg_to_normal_operation_shuffle(shuffle_save); + } +} + +static void dramc_impedance_tracking_enable(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl0, + MISC_CTRL0_IMPCAL_CHAB_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_HW, 1, + MISC_IMPCAL_IMPCAL_EN, 0, + MISC_IMPCAL_IMPCAL_SWVALUE_EN, 1, + MISC_IMPCAL_IMPCAL_NEW_OLD_SL, 1, + MISC_IMPCAL_IMPCAL_DRVUPDOPT, 1, + MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT, 1, + MISC_IMPCAL_IMPCAL_SM_ECO_OPT, 1, + MISC_IMPCAL_IMPBINARY, 1, + MISC_IMPCAL_DRV_ECO_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl0, + MISC_CTRL0_IMPCAL_LP_ECO_OPT, 0x1, + MISC_CTRL0_IMPCAL_TRACK_DISABLE, chn); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 1); + } + + SET32_BITFIELDS(&ch[0].phy_ao.misc_impcal, + MISC_IMPCAL_DIS_SUS_CH0_DRV, 0, + MISC_IMPCAL_DIS_SUS_CH1_DRV, 1, + MISC_IMPCAL_IMPSRCEXT, 0, + MISC_IMPCAL_IMPCAL_ECO_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_impcal, + MISC_IMPCAL_DIS_SUS_CH0_DRV, 1, + MISC_IMPCAL_DIS_SUS_CH1_DRV, 0, + MISC_IMPCAL_IMPSRCEXT, 1, + MISC_IMPCAL_IMPCAL_ECO_OPT, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_DRVCGWREF, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_DQDRVSWUPD, 1); + } +} + +static void dramc_impedance_hw_saving(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_HWSAVE_EN, 1); +} + +static void switch_hmr4(const struct ddr_cali* cali, bool en) +{ + u8 tog_opt = (en && cali->support_ranks == DUAL_RANK_DDR) ? 1 : 0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.ref_bounce2, REF_BOUNCE2_PRE_MR4INT_TH, 5); + SET32_BITFIELDS(&ch[chn].ao.refctrl2, REFCTRL2_MR4INT_TH, 5); + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_TOG_OPT, tog_opt); + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFRDIS, !en); + } +} + +static void dramc_refresh_rate_debounce_enable(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.ref_bounce1, + REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT, 0x4, + REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 5, + REF_BOUNCE1_REFRATE_DEBOUNCE_OPT, 0, + REF_BOUNCE1_REFRATE_DEBOUNCE_DIS, 0xff1f); +} + +static void enable_dfs_no_queue_flush(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_HWSET_WLRL, 0, + DVFS_CTRL0_DVFS_RXFIFOST_SKIP, 0, + DVFS_CTRL0_DVFS_NOQUEFLUSH_EN, 1, + DVFS_CTRL0_R_DMDVFSMRW_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.shuctrl1, + SHUCTRL1_FC_PRDCNT, 0, + SHUCTRL1_CKFSPE_PRDCNT, 0, + SHUCTRL1_VRCGEN_PRDCNT, 0, + SHUCTRL1_CKFSPX_PRDCNT, 0); + SET32_BITFIELDS(&ch[chn].ao.bypass_fspop, + BYPASS_FSPOP_BPFSP_OPT, 0); + } +} + +static void _dramc_dqs_precalculation_preset(u8 chn, u8 rk, u8 b) +{ + u8 mck, ui, pi, mck_p1, ui_p1, write_ui, write_pi; + const u8 mck2ui = 4; + + if (b == 0) { + mck = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0); + ui = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0); + mck_p1= READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0); + ui_p1 = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0); + pi = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + + write_ui = (mck << mck2ui) + ui; + write_pi = (mck_p1 << mck2ui) + ui_p1; + SET32_BITFIELDS(&ch[chn].phy_ao.byte[b].rk[rk].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, write_ui, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, pi); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[b].rk[rk].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, write_ui, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, write_pi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, pi); + } else { + mck = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1); + ui = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1); + mck_p1= READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1); + ui_p1 = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1); + pi = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + + write_ui = (mck << mck2ui) +ui; + write_pi = (mck_p1 << mck2ui) + ui_p1; + SET32_BITFIELDS(&ch[chn].phy_ao.byte[b].rk[rk].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, write_ui, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, pi); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[b].rk[rk].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, write_ui, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, write_pi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, pi); + } +} + +void dramc_dqs_precalculation_preset(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + + for (u8 byte = 0; byte < DQS_NUMBER; byte++) + for (u8 rank = RANK_0; rank < cali->support_ranks; rank++) + _dramc_dqs_precalculation_preset(chn, rank, byte); + + if (get_shu(cali) == DRAM_DFS_SHU6) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_pre_tdqsck, + SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 0x1); + } else { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_pre_tdqsck, + SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 0x0); + } +} + +void xrtwtw_shu_setting(const struct ddr_cali* cali) +{ + u8 byte, chn; + u16 tx_dly_oen_rk[2][2] = {0}, tx_pi_upd[2] = {0}; + u16 tx_rank_inctl, tx_dly_oen_rk_max, tx_pi_upd_max; + + dram_freq_grp freq_group = get_freq_group(cali); + chn = cali->chn; + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + tx_dly_oen_rk[rk][0] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); + tx_dly_oen_rk[rk][1] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); + } + + for (byte = 0; byte < DQS_NUMBER; byte++) { + tx_dly_oen_rk_max = (tx_dly_oen_rk[0][byte] > tx_dly_oen_rk[1][byte]) ? + tx_dly_oen_rk[0][byte]: tx_dly_oen_rk[1][byte]; + if (freq_group >= DDRFREQ_1200) + tx_pi_upd[byte] = (tx_dly_oen_rk_max > 2) ? (tx_dly_oen_rk_max - 2) : 0; + else + tx_pi_upd[byte] = (tx_dly_oen_rk_max > 1) ? (tx_dly_oen_rk_max - 1) : 0; + } + + tx_pi_upd_max = (tx_pi_upd[0] > tx_pi_upd[1]) ? tx_pi_upd[0] : tx_pi_upd[1]; + tx_rank_inctl = (tx_pi_upd_max > 1) ? (tx_pi_upd_max - 1) : 0; + + SET32_BITFIELDS(&ch[chn].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, tx_pi_upd[0], + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, tx_pi_upd[1]); + + SET32_BITFIELDS(&ch[chn].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0, + SHU_TX_RANKCTL_TXRANKINCTL, tx_rank_inctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, tx_rank_inctl); +} + +static void dpm_control_init(const struct ddr_cali *cali) +{ + u8 val, pll1_val, pll2_val; + u8 shu_sram = get_shu(cali); + u8 pll_mode = *(cali->pll_mode); + + + val = 0x3; + SET32_BITFIELDS(&mtk_dpm->low_power_cfg_0, + LPIF_LOW_POWER_CFG_0_PHYPLL_EN, val, + LPIF_LOW_POWER_CFG_0_DPY_DLL_EN, val, + LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN, val, + LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN, val, + LPIF_LOW_POWER_CFG_0_DPY_VREF_EN, val); + SET32_BITFIELDS(&mtk_dpm->low_power_cfg_3, + LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN, val, + LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN, val, + LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN, val); + + if (pll_mode == PHYPLL_MODE) { + dramc_dbg("PHYPLL\n"); + pll1_val = val; + pll2_val = 0; + } else { + dramc_dbg("CLRPLL\n"); + pll1_val = 0; + pll2_val = val; + } + + SET32_BITFIELDS(&mtk_dpm->low_power_cfg_0, + LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN, pll1_val, + LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW, pll1_val, + LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN, pll2_val, + LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW, pll2_val); + SET32_BITFIELDS(&mtk_dpm->fsm_cfg_1, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL, 0x0, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND, 0x0, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR, 0x0, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND, 0x0, + LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW, 0x1, + LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND, 0x1, + LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL, 0x1, + LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND, 0x1); + SET32_BITFIELDS(&mtk_dpm->fsm_out_ctrl_0, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW, 0x1); + + shu_sram |= shu_sram << 4; + SET32_BITFIELDS(&mtk_dpm->low_power_cfg_1, + LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL, shu_sram); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, + PHYPLL0_RG_RPHYPLL_EN, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, + CLRPLL0_RG_RCLRPLL_EN, 0x0); + } + SET32_BITFIELDS(&mtk_dpm->dfd_dbug_0, + LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN, 0x1); +} + +void dramc_runtime_config(const struct ddr_cali* cali) +{ + dpm_control_init(cali); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.refctrl1, + REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 0x1); + dramc_dbg("REFRESH_OVERHEAD_REDUCTION: ON\n"); + + dramc_dqs_precalculation_enable(); + dramc_dbg("DQS Precalculation for DVFS: ON\n"); + + dramc_hw_gating_debug(true); + dramc_dbg("HW_GATING DBG: ON\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.zq_set1, ZQ_SET1_ZQCALDISB, 1); + dramc_dbg("ZQCS_ENABLE_LP4: ON\n"); + + tx_picg_new_mode_enable(); + dramc_dbg("TX_PICG_NEW_MODE: ON\n"); + + enable_phy_dcm_non_shuffle(DCM_ON); + dramc_dbg("LOWPOWER_GOLDEN_SETTINGS(DCM): ON\n"); + + dramc_shu_tracking_dcm_en_by_sram(cali); + + dramc_impedance_tracking_enable(); + dramc_dbg("IMPEDANCE_TRACKING: ON\n"); + dramc_impedance_hw_saving(); + + switch_hmr4(cali, true); + dramc_dbg("TEMP_SENSOR: ON\n"); + + dramc_dbg("Refresh Rate DeBounce: ON\n"); + dramc_refresh_rate_debounce_enable(); + + enable_dfs_no_queue_flush(); + dramc_dbg("DFS_NO_QUEUE_FLUSH: ON\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, 0x0); + + dramc_dbg("DDR_RESERVE_NEW_MODE: ON\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ddr_reserve, + MISC_DDR_RESERVE_WDT_LITE_EN, 1, + MISC_DDR_RESERVE_WDT_SM_CLR, 0); +}