[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add option to enable/disable EIST

[Subrata Banik (Code Review)]

Hello Aaron Durbin, build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

https://review.coreboot.org/19676

to look at the new patch set (#2).

Change subject: soc/intel/skylake: Add option to enable/disable EIST
......................................................................

soc/intel/skylake: Add option to enable/disable EIST

Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.

Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/cpu.c
4 files changed, 19 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/19676/2