Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... File src/mainboard/google/sarien/ramstage.c:
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... PS3, Line 83: ssd_reset
maybe ssd_deassert_reset() to be clear what it is doing.
Done
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... PS3, Line 85: GPP_H12
Since this is used in multiple places it is probably a good idea to add something to variant/gpio. […]
Done
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... PS3, Line 87:
extra newline
Done
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/romstage... PS3, Line 67: ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)
soc/intel/cannonlake/pmutil. […]
Done
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/romstage... PS3, Line 69: 75
Make this a #define. […]
HW engineer said 50ms should be okay, so I reduced it. If we can have 2 early gpio tables (warm reset / cold reset), we could potentially get rid of this delay, but that will require more testing. I wasn't able to detect warm/cold reset when setting early gpio tables, need to check that as well.