Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5063
-gerrit
commit 41dafa1436605712a844fd1eccccc70fb594142a Author: Aaron Durbin adurbin@chromium.org Date: Thu Jan 23 22:44:15 2014 -0600
baytrail: add option for enabling PS2 mode
The VNN and VCC regulator for baytrail can enter into PS2 mode under low power conditions to save regulator power. This is available for >C0 parts. Add a device tree option to enable PS2 for the VCC and VNN rails.
BUG=chrome-os-partner:24542 BRANCH=baytrail TEST=Built and booted b3.
Change-Id: Iea952b17ca77ac42f34285b2d171e566b755e002 Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: https://chromium-review.googlesource.com/183595 --- src/soc/intel/baytrail/baytrail/iosf.h | 2 ++ src/soc/intel/baytrail/chip.h | 4 ++++ src/soc/intel/baytrail/romstage/pmc.c | 36 +++++++++++++++++++++++++++++----- 3 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index e936072..d498dd0 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -231,6 +231,8 @@ void iosf_ssus_write(int reg, uint32_t val); # define SB_BIOS_CONFIG_PDM_MODE (1 << 16) # define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) # define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) +# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) +# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) # define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) # define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) #define BIOS_RESET_CPL 0x05 diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 955ecb0..774f076 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -31,6 +31,10 @@ struct soc_intel_baytrail_config { uint8_t ide_legacy_combined; uint8_t clkreq_enable;
+ /* VR low power settings -- enable PS2 mode for gfx and core */ + int vnn_ps2_enable; + int vcc_ps2_enable; + /* USB Port Disable mask */ uint16_t usb2_port_disable_mask; uint16_t usb3_port_disable_mask; diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 6bd7805..a72e159 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -19,11 +19,16 @@
#include <stddef.h> #include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> #include <baytrail/iomap.h> #include <baytrail/iosf.h> +#include <baytrail/lpc.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> #include <baytrail/romstage.h> +#include "../chip.h"
void tco_disable(void) { @@ -38,13 +43,34 @@ void tco_disable(void) void punit_init(void) { uint32_t reg; + uint8_t rid; + const struct device *dev; + const struct soc_intel_baytrail_config *cfg = NULL;
+ rid = pci_read_config8(IOSF_PCI_DEV, REVID); + dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)); + + if (dev) + cfg = dev->chip_info; + + reg = iosf_punit_read(SB_BIOS_CONFIG); /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ - reg = SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; - pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | - IOSF_REG(SB_BIOS_CONFIG) | IOSF_BYTE_EN_2; - pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); + reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; + /* Configure VR low power mode for C0 and above. */ + if (rid >= RID_C_STEPPING_START && cfg != NULL && + (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) { + printk(BIOS_DEBUG, "Enabling VR PS2 mode: "); + if (cfg->vnn_ps2_enable) { + reg |= SB_BIOS_CONFIG_PS2_EN_VNN; + printk(BIOS_DEBUG, "VNN "); + } + if (cfg->vcc_ps2_enable) { + reg |= SB_BIOS_CONFIG_PS2_EN_VCC; + printk(BIOS_DEBUG, "VCC "); + } + printk(BIOS_DEBUG, "\n"); + } + iosf_punit_write(SB_BIOS_CONFIG, reg);
/* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE;