5 Oct
2020
5 Oct
'20
10:03 a.m.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45914 )
Change subject: nb/intel/i945/memmap.c: Use `postcar_enable_tseg_cache` ......................................................................
Patch Set 2: Code-Review-2
On hold until the purpose of caching what is marked as TSEG is clear. This might have to do with the stage cache.
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Gerrit-Project: coreboot
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