[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup...

[Xi Chen (Code Review)]

Attention is currently required from: Hung-Te Lin, CK HU, Yidi Lin.
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44730 )

Change subject: soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup time
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Patch Set 47:

(1 comment)

Patchset:

PS47:
> @Yidi/XiXi, was this included in our latest dram vendor code?

Yes, already included in latest dram vendor code.