24 Dec
2021
24 Dec
'21
10:23 p.m.
Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60316 )
Change subject: soc/mediatek/mt8186: adjust usage of SRAM L2C ......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60316/comment/84738c5c_4e2bcfc9 PS4, Line 8: Please describe the problem at hand.
https://review.coreboot.org/c/coreboot/+/60316/comment/03339845_76d598dc PS4, Line 9: However the BootROM : has configured only half of L2/L3 cache as SRAM. Is that a bug? Can the BootROM be fixed?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2
Gerrit-Change-Number: 60316
Gerrit-PatchSet: 4
Gerrit-Owner: Rex-BC Chen rex-bc.chen@mediatek.com
Gerrit-Reviewer: Hung-Te Lin hungte@chromium.org
Gerrit-Reviewer: Rex-BC Chen rex-bc.chen@mediatek.com
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Gerrit-CC: Paul Menzel paulepanter@mailbox.org
Gerrit-Attention: Hung-Te Lin hungte@chromium.org
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Gerrit-Comment-Date: Fri, 24 Dec 2021 20:23:27 +0000
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