Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43775 )
Change subject: src: Never set ISA Enable on PCI bridges ......................................................................
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There is some more: AIUI, this bit relates to the avoidance of 0x100..0x3ff ranges in the v3 allocator. Which was dropped in v4. I assume if there were >256 ports resources below a bridge, the v4 allocator would allocate in a range that is later broken by setting this bit.
Should we see if it breaks and react if it does? Basically, let this go and see what happens.
I can try plugging in a few cards into the Asrock B85M Pro4 and see if it survives.
Log: https://dpaste.com/47X6KH8SL.txt
With the following local tree commits: * cd9edb3c37 (HEAD -> master) nb/intel/haswell: Configure VCs on Egress Port * 506e15a7e1 [NOTFORMERGE] mb/asrock/b85m_pro4/devicetree.cb: Make Windows 10 boot * 322bf1785b nb/intel/haswell: Add RMRR for USB devices * fa405dc028 haswell: Report only one HPET timer device * ec05106662 sb/intel/lynxpoint: Add debug print * bae9c0974f src: Never set ISA Enable on PCI bridges * eed8ae9c4e device/pci_device.c: Do not complain about disabled devices * 83d3ca5248 haswell: Set up Root Complex topology * 78b6bfdaec nb/intel/haswell: Enable DMI ASPM * d54c9b0fef (origin/master, origin/HEAD) mb/google/dedede/var/waddledoo: Configure stop delay for SiS TS