Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69209 )
Change subject: soc/amd/common/include/gpio_defs.h: Add comment for accuracy ......................................................................
soc/amd/common/include/gpio_defs.h: Add comment for accuracy
The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times slightly.
Time PCO Others 1mS 0.915mS 1.220mS 2mS 2.013mS 2.684mS
Signed-off-by: Fred Reitberger reitbergerfred@gmail.com Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/69209/1
diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 187be51..718a45c 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -113,6 +113,7 @@ #define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT)
#define GPIO_TIMEBASE_61uS 0 +/* The next value is only 183uS on Picasso. It is 244uS on Cezanne and later SoCs */ #define GPIO_TIMEBASE_183uS (1 << 4) #define GPIO_TIMEBASE_15560uS (1 << 7) #define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | GPIO_TIMEBASE_15560uS)