[coreboot-gerrit] Change in coreboot[master]: sb/intel/ibexpeak/early_thermal.c: Reduce difference with bd82x6x

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61664 )

Change subject: sb/intel/ibexpeak/early_thermal.c: Reduce difference with bd82x6x
......................................................................

sb/intel/ibexpeak/early_thermal.c: Reduce difference with bd82x6x

Change-Id: I470957b395f1010668f1c9d2c2c6ae7cb88e89a7
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/ibexpeak/early_thermal.c
1 file changed, 19 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/61664/1

diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c
index d8b9195..0accfc6 100644
--- a/src/southbridge/intel/ibexpeak/early_thermal.c
+++ b/src/southbridge/intel/ibexpeak/early_thermal.c
@@ -6,35 +6,33 @@
 #include "cpu/intel/model_2065x/model_2065x.h"
 #include <cpu/x86/msr.h>

+/* Temporary address for the thermal BAR */
+#define TBARB_TEMP 0x40000000
+
 /* Early thermal init, must be done prior to giving ME its memory
-   which is done at the end of raminit.  */
+   which is done at the end of raminit */
 void early_thermal_init(void)
 {
-	pci_devfn_t dev;
-	msr_t msr;
-
+	const pci_devfn_t dev;
    dev = PCI_DEV(0x0, 0x1f, 0x6);

-	/* Program address for temporary BAR.  */
-	pci_write_config32(dev, 0x40, 0x40000000);
+	/* Program address for temporary BAR */
+	pci_write_config32(dev, 0x40, TBARB_TEMP);
    pci_write_config32(dev, 0x44, 0x0);

-	/* Activate temporary BAR.  */
-	pci_write_config32(dev, 0x40,
-			   pci_read_config32(dev, 0x40) | 5);
+	/* Activate temporary BAR */
+	pci_or_config32(dev, 0x40, 5);

-	/* Perform init.  */
-	/* Configure TJmax.  */
-	msr = rdmsr(MSR_TEMPERATURE_TARGET);
-	write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6);
-	/* Northbridge temperature slope and offset.  */
-	write16((u16 *)0x40000016, 0x7746);
-	/* Enable thermal data reporting, processor, PCH and northbridge.  */
-	write16((u16 *)0x4000001a,
-		(read16((u16 *)0x4000001a) & ~0xf) | 0x10f0);
+	/* Perform init */
+	/* Configure TJmax */
+	const msr_t msr = rdmsr(MSR_TEMPERATURE_TARGET);
+	write16p(TBARB_TEMP + 0x12, ((msr.lo >> 16) & 0xff) << 6);
+	/* Northbridge temperature slope and offset */
+	write16p(TBARB_TEMP + 0x16, 0x7746);
+	/* Enable thermal data reporting, processor, PCH and northbridge */
+	write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0);

-	/* Disable temporary BAR.  */
-	pci_write_config32(dev, 0x40,
-			   pci_read_config32(dev, 0x40) & ~1);
+	/* Disable temporary BAR */
+	pci_and_config32(dev, 0x40, ~1);
    pci_write_config32(dev, 0x40, 0);
 }