Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43741 )
Change subject: Enable long cr50 ready pulses for Tigerlake systems ......................................................................
Patch Set 7:
(2 comments)
I have moved the code out of the vboot directory.
I still think it is a superior solution to communicate with cr50 about the new register only once during boot, rather than dropping the CBMEM and reading the version/register again in early ramstage.
https://review.coreboot.org/c/coreboot/+/43741/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43741/2//COMMIT_MSG@15 PS2, Line 15: to FSP. For Volteer (and future Tigerlake boards) we enable mode S0i3.4
The very first proposal, was to add the functionality without adding one more point at which the AP […]
Regarding Julius' alternative proposal, of moving all the ramstage cr50 communication to be earlier than FSP-S. As far as I can tell, the existing cr50 communication in ramstage is already declared as BS_ON_ENTRY in cr50_enable_update.c, and still, it runs after the FSP-S. (I attempted switching it to BS_PRE_DEVICE, but that did not cause it to run before FSP-S.)
https://review.coreboot.org/c/coreboot/+/43741/2/src/security/vboot/vboot_lo... File src/security/vboot/vboot_logic.c:
https://review.coreboot.org/c/coreboot/+/43741/2/src/security/vboot/vboot_lo... PS2, Line 304: set_cr50_board_cfg();
This is a good point, I will work on that...
Done