Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47983/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47983/2//COMMIT_MSG@8 PS2, Line 8: Can you please add a brief description of why the change is being made.
Also, BUG=b:???
https://review.coreboot.org/c/coreboot/+/47983/2/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47983/2/src/soc/intel/common/block/... PS2, Line 412: mov %ecx, %eax This doesn't look right. It is writing # of LLC ways to the mask. But, you need to set all the bits in MASK_1 to 1.
https://review.coreboot.org/c/coreboot/+/47983/2/src/soc/intel/common/block/... PS2, Line 418: Program MSR 0x1892 IA32_CR_SF_QOS_MASK_2 with : * total number of LLC ways This doesn't match the recommendation. Is this intentional?