[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60180 )

Change subject: soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function
......................................................................

soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function

The PMC IPC method used to enable/disable PCIe srcclks uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak 
Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147
---
M src/soc/intel/alderlake/pcie_rp.c
1 file changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/60180/1

diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c
index dd0cfbc..26ce785 100644
--- a/src/soc/intel/alderlake/pcie_rp.c
+++ b/src/soc/intel/alderlake/pcie_rp.c
@@ -6,6 +6,8 @@
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>

+#define CPU_CPIE_VW_IDX_BASE	24
+
 static const struct pcie_rp_group pch_lp_rp_groups[] = {
    { .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
    { .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4 },
@@ -91,3 +93,20 @@

return PCIE_RP_UNKNOWN;
 }
+
+int soc_get_cpu_rp_vw_idx(const struct device *dev)
+{
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return -1;
+
+	switch (dev->path.pci.devfn) {
+	case SA_DEVFN_CPU_PCIE1_0:
+		return CPU_CPIE_VW_IDX_BASE;
+	case SA_DEVFN_CPU_PCIE6_0:
+		return CPU_CPIE_VW_IDX_BASE + 3;
+	case SA_DEVFN_CPU_PCIE6_2:
+		return CPU_CPIE_VW_IDX_BASE + 2;
+	default:
+		return -1;
+	}
+}