Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42566 )
Change subject: util/amdfwtool: Add support for EFS SPI values for F17h and F15h ......................................................................
util/amdfwtool: Add support for EFS SPI values for F17h and F15h
The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morpheus.
Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com --- M util/amdfwtool/amdfwtool.c 1 file changed, 100 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/42566/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index a5e5110..0241ba2 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -215,7 +215,14 @@ printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n"); printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); + printf("-C | --soc-family <HEX_VAL> Specify SOC Family\n"); + printf("-D | --soc-model-min <HEX_VAL> Specify minimum SOC Model support\n"); + printf("-E | --soc-model-max <HEX_VAL> Specify maximum SOC Model support\n"); printf("-h | --help show this help\n"); + printf("\Embedded Firmware Structure options:\n"); + printf("--spi-speed <HEX_VAL> SPI speed to place in EFS Table\n"); + printf("--spi-read-mode <HEX_VAL> SPI read mode to place in EFS Table\n"); + printf("--spi-micron-flag <HEX_VAL> SPI Micron override flag to place in EFS Table\n"); }
typedef enum _amd_bios_type { @@ -413,7 +420,26 @@ uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; - uint32_t reserved[0x2c]; /* 0x24 - 0x4f */ + uint32_t second_gen_efs; + uint32_t bios3_entry; + uint32_t reserved_2Ch; + uint32_t promontory_fw_ptr; + uint32_t lp_promontory_fw_ptr; + uint32_t reserved_38h; + uint32_t reserved_3Ch; + uint8_t spi_readmode_f15_mod_60_6f; + uint8_t fast_speed_new_f15_mod_60_6f; + uint8_t reserved_42h; + uint8_t spi_readmode_f17_mod_00_2f; + uint8_t spi_fastspeed_f17_mod_00_2f; + uint8_t qpr_dummy_cycle_f17_mod_00_2f; + uint8_t reserved_46h; + uint8_t spi_readmode_f17_mod_30_3f; + uint8_t spi_fastspeed_f17_mod_30_3f; + uint8_t micron_detect_f17_mod_30_3f; + uint8_t reserved_4Ah; + uint8_t reserved_4Bh; + uint32_t reserved_4Ch; } __attribute__((packed, aligned(16))) embedded_firmware;
typedef struct _psp_directory_header { @@ -1038,8 +1064,18 @@
fill_dir_header(biosdir, count, cookie); } -// Unused values: CDE -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:"; + +enum { + /* begin after ASCII characters */ + LONGOPT_FAMILY = 256, + LONGOPT_MODEL = 257, + LONGOPT_SPI_READ_MODE = 258, + LONGOPT_SPI_SPEED = 259, + LONGOPT_SPI_MICRON_FLAG = 260, +}; + +// Use non-ASCII values for additional input parameters +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:D:E:";
static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1086,6 +1122,10 @@ {"mp2-config", required_argument, 0, 'X' }, {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, + /* Embedded Firmware Structure items*/ + {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, + {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, + {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, /* other */ {"output", required_argument, 0, 'o' }, {"flashsize", required_argument, 0, 'f' }, @@ -1093,6 +1133,9 @@ {"anywhere", no_argument, 0, 'q' }, {"sharedmem", required_argument, 0, 'R' }, {"sharedmem-size", required_argument, 0, 'P' }, + {"soc-family", required_argument, 0, 'C' }, + {"soc-model-min", required_argument, 0, 'D' }, + {"soc-model-max", required_argument, 0, 'E' }, {"help", no_argument, 0, 'h' }, {NULL, 0, 0, 0 } }; @@ -1200,6 +1243,13 @@ bool any_location = 0; uint32_t romsig_offset; uint32_t rom_base_address; + uint8_t soc_family = 0; + uint8_t soc_model_min = 0; + uint8_t soc_model_max = 0; + uint8_t efs_spi_readmode = 0xff; + uint8_t efs_spi_speed = 0xff; + uint8_t efs_spi_micron_flag = 0xff; + int multi = 0;
while (1) { @@ -1394,6 +1444,30 @@ register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); sub = instance = 0; break; + case 'C': + soc_family = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case 'D': + soc_model_min = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case 'E': + soc_model_max = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_READ_MODE: + efs_spi_readmode = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_SPEED: + efs_spi_speed = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_MICRON_FLAG: + efs_spi_micron_flag = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; case 'o': output = optarg; break; @@ -1455,6 +1529,11 @@ retval = 1; }
+ if (soc_model_min > soc_model_max) { + printf("Error: Invalid SOC model range.\n\n"); + retval = 1; + } + if (retval) { usage(); return retval; @@ -1512,6 +1591,24 @@ amd_romsig->gec_entry = 0; amd_romsig->xhci_entry = 0;
+ if (soc_family == 0x15 && soc_model_min >= 0x60 && soc_model_max <= 0x6f) { + amd_romsig->second_gen_efs = 0; + amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; + amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; + } + if (soc_family == 0x17 && soc_model_min >= 0x0 && soc_model_max <= 0x2f) { + amd_romsig->second_gen_efs = 0; + amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; + amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; + amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = efs_spi_micron_flag; + } + if (soc_family == 0x17 && soc_model_min >= 0x30 && soc_model_max <= 0x3f) { + amd_romsig->second_gen_efs = 1; + amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; + amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; + amd_romsig->micron_detect_f17_mod_30_3f = efs_spi_micron_flag; + } + integrate_firmwares(&ctx, amd_romsig, amd_fw_table);
ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */