[coreboot-gerrit] [S] Change in coreboot[main]: mb/google/brox: Enable PMC pins to work with PD

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81207?usp=email )

Change subject: mb/google/brox: Enable PMC pins to work with PD
......................................................................

mb/google/brox: Enable PMC pins to work with PD

Enable SMLINK1 interface for PMC-PD communication to configure Type-C
muxes.

Refer RPL EDS vol 1: 765585.

BUG=b:327622474
BRANCH=None
TEST=Boot image on SKU2 and check PMC-PD working.

Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10
Signed-off-by: Ashish Kumar Mishra 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81207
Reviewed-by: Eric Lai 
Tested-by: build bot (Jenkins) 
Reviewed-by: Deepti Deshatty 
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
1 file changed, 6 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved
  Deepti Deshatty: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 2ee4d08..9bdc197 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -102,8 +102,8 @@
    PAD_NC(GPP_B7, NONE),
    /* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> SOC_I2C3_SCL (NC) */
    PAD_NC(GPP_B8, NONE),
-	/* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> SOC_I2C_PD_INT_ODL (NC) */
-	PAD_NC(GPP_B11, NONE),
+	/* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> SOC_I2C_PD_INT_ODL */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
    /* GPP_B12 : [NF1: SLP_S0# NF6: USB_C_GPP_B12] ==> SLP_S0_R_L */
    PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
    /* GPP_B13 : [NF1: PLTRST# NF6: USB_C_GPP_B13] ==> PLT_RST_L */
@@ -134,10 +134,10 @@
    PAD_NC(GPP_C4, NONE),
    /* GPP_C5 : [NF1: SML0ALERT# NF6: USB_C_GPP_C5] ==> SOC_GPP_C5_BOOT_STRAP0 (NC) */
    PAD_NC(GPP_C5, NONE),
-	/* GPP_C6 : SML1CLK ==> SOC_I2C_PD_SCL (NC) */
-	PAD_NC(GPP_C6, NONE),
-	/* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA (NC) */
-	PAD_NC(GPP_C7, NONE),
+	/* GPP_C6 : SML1CLK ==> SOC_I2C_PD_SCL */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+	/* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),

/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */
    PAD_CFG_GPI_APIC_LOW(GPP_D0, NONE, PLTRST),