31 Oct
2024
31 Oct
'24
9 a.m.
Attention is currently required from: Curtis Chen, David Ruth, Jamie Chen, Lawrence Chang, Nick Vaccaro, Simon Yang.
Paul Menzel has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/84866?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/intel/jasperlake: add support for RP LTR mechanism ......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84866/comment/1eaf7e2b_9ee8bb85?usp... : PS3, Line 13: Tested on Awasuki with RTL8852BE How to check this exactly? coreboot logs or `lspci`?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f
Gerrit-Change-Number: 84866
Gerrit-PatchSet: 3
Gerrit-Owner: Lawrence Chang lawrence.chang@intel.com
Gerrit-Reviewer: Curtis Chen curtis.chen@intel.com
Gerrit-Reviewer: David Ruth druth@chromium.org
Gerrit-Reviewer: David Ruth druth@google.com
Gerrit-Reviewer: Jamie Chen jamie.chen@intel.com
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Gerrit-Comment-Date: Thu, 31 Oct 2024 08:00:47 +0000
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