[coreboot-gerrit] [M] Change in coreboot[master]: soc/intel/xeon_sp: add MSR definition for SPR-SP

[Jian-Ming Wang (Code Review)]

Attention is currently required from: TimLiu-SMCI, Jonathan Zhang, Johnny Lin, David Hendricks, Christian Walter, Arthur Heymans, Tim Chu.

Jian-Ming Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72611 )

Change subject: soc/intel/xeon_sp: add MSR definition for SPR-SP
......................................................................

Patch Set 1:

(1 comment)

File src/soc/intel/xeon_sp/include/soc/msr.h:

https://review.coreboot.org/c/coreboot/+/72611/comment/2e85a9e1_85614fde 
PS1, Line 44: #if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP))
> Sounds good to me

Agreed. The problems found by David is due to spr has different arrangement of registers with previous platforms. Using #if to maintain all discrepancies in a single header might not friendly for maintenance and code review.

// In msr.h
 #if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP))
   #include <soc/msr_spr.h>
 #elif (CONFIG(SOC_INTEL_COOPERLAKE_SP))
   #include <soc/msr_cpx.h>
 #elif (CONFIG(SOC_INTEL_SKYLAKE_SP))
   #include <soc/msr_skx.h>
 #endif