[coreboot-gerrit] [M] Change in coreboot[master]: mb/google,intel: Use common ChromeEC code for SMI APMC

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Subrata Banik, Matt DeVillier, Karthik Ramasubramanian, Felix Held.

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74513 )

Change subject: mb/google,intel: Use common ChromeEC code for SMI APMC
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Patch Set 3:

(1 comment)

Patchset:

PS3:
> would be good to test this one on hardware, since this will have google_chromeec_get_mkbp_event call […]

Right, I missed the added MKBP here, but noticed in CB:74603 for the chromeec_smi_sleep() case and left it as [WIP] for this exact reason.

Related: CB:15685 and CB:22005. Latter describes "adding EC debug logs" as a verification and test.

So what would be the minimal required hardware testing for this? The first APMC that would reach the changed code is late ramstage, device init calls apm_control() with APM_CNT_ACPI_DISABLE or _ENABLE. Just getting past that with one of the boards without regression is enough?