[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56177 )

Change subject: soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared
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soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared

The Majolica UEFI ACPI tables have this listed as shared. It's already a
level interrupt, so no reason it shouldn't be shared.

This change makes it so Windows can correctly initialize the GPIO
controller.

BUG=b:186212501
TEST=Boot guybrush to windows and see GPIO controller functional. Also
boot guybrush to windows and verify GPIO controller still works.

Signed-off-by: Raul E Rangel 
Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56177
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/soc/amd/cezanne/acpi/mmio.asl
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl
index 7b49b85..6126843 100644
--- a/src/soc/amd/cezanne/acpi/mmio.asl
+++ b/src/soc/amd/cezanne/acpi/mmio.asl
@@ -34,7 +34,7 @@
    			ResourceConsumer,
    			Level,
    			ActiveLow,
-				Exclusive, , , IRQR)
+				Shared, , , IRQR)
    		{ 0 }
    		Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
    	}