Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36100 )
Change subject: soc/intel/common: lpc/espi: fix wrong lock bit ......................................................................
soc/intel/common: lpc/espi: fix wrong lock bit
This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance with doc#332691-003EN and doc#334819-001.
Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/common/block/lpc/lpc_def.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36100/1
diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index c066f68..9a72580 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -37,7 +37,7 @@ #define LPC_LGMR_WINDOW_SIZE (64 * KiB) #define LPC_BIOS_CNTL 0xdc #define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 2) /* LE */ +#define LPC_BC_LE (1 << 1) /* LE */ #define LPC_BC_EISS (1 << 5) /* EISS */ #define LPC_PCCTL 0xE0 /* PCI Clock Control */ #define LPC_PCCTL_CLKRUN_EN (1 << 0)