Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6063
-gerrit
commit 6c3dd0835ac1b1e4988fd73a89ff628d4f8d15cf Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon Jun 16 09:14:49 2014 +0300
sandy/ivy boards: Use acpi_s3_resume_allowed()
Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/google/butterfly/romstage.c | 21 +++++++++++---------- src/mainboard/google/link/romstage.c | 21 +++++++++++---------- src/mainboard/google/parrot/romstage.c | 21 +++++++++++---------- src/mainboard/google/stout/romstage.c | 21 +++++++++++---------- src/mainboard/intel/emeraldlake2/romstage.c | 21 +++++++++++---------- src/mainboard/kontron/ktqm77/romstage.c | 21 +++++++++++---------- src/mainboard/lenovo/t520/romstage.c | 21 +++++++++++---------- src/mainboard/lenovo/t530/romstage.c | 21 +++++++++++---------- src/mainboard/lenovo/x230/romstage.c | 21 +++++++++++---------- src/mainboard/samsung/lumpy/romstage.c | 21 +++++++++++---------- src/mainboard/samsung/stumpy/romstage.c | 21 +++++++++++---------- 11 files changed, 121 insertions(+), 110 deletions(-)
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index d32f3f0..d946ea3 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -28,6 +28,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" @@ -207,16 +208,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
post_code(0x38); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f17880..18c833a 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -29,6 +29,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" @@ -244,16 +245,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } } else { /* This is the fastest way to let users know * the Intel CPU is now alive. diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 1799aec..45cf7fe 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -28,6 +28,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" @@ -207,16 +208,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
post_code(0x38); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index f53c07d..0e29b33 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -28,6 +28,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" @@ -254,16 +255,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
/* Do ec reset as early as possible, but skip it on S3 resume */ diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index a7ab482..5597a2d 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -27,6 +27,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include "superio/smsc/sio1007/chip.h" @@ -255,16 +256,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
post_code(0x38); diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 7385cd0..09fd634 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -27,6 +27,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" @@ -258,16 +259,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
post_code(0x38); diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index a2c3778..548c040 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -29,6 +29,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> @@ -211,16 +212,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
post_code(0x38); diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 96b5205..d65031a 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -29,6 +29,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" @@ -211,16 +212,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
post_code(0x38); diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 6e4e685..8441db3 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -29,6 +29,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" @@ -201,16 +202,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
post_code(0x38); diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index ef5a836..001a1f8 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -29,6 +29,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <cbfs.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include <bootmode.h> @@ -230,16 +231,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
post_code(0x38); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 0ae71a8..6ab7007 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -28,6 +28,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include <bootmode.h> @@ -271,16 +272,16 @@ void main(unsigned long bist) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } }
post_code(0x38);