Felix Held (felix-coreboot@felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12353
-gerrit
commit 488ce6d347c78e42ab0c7a7d5dd20efafb47a29e Author: Felix Held felix-coreboot@felixheld.de Date: Fri Nov 6 18:32:43 2015 +0100
pcengines/apu1: enable use of clkreq pins
only enable pcie gpp clocks when the corresponding clkreq pin is asserted
Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- src/mainboard/pcengines/apu1/mainboard.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 82cf992..f91e879 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -187,10 +187,10 @@ static void mainboard_enable(device_t dev) u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); /* GPP CLK0-2 are connected to the 3 ethernet chips * GPP CLK3-4 are connected to the miniPCIe slots */ - write8(misc_mem_clk_cntrl + 0, 0xFF); - write8(misc_mem_clk_cntrl + 1, 0xFF); + write8(misc_mem_clk_cntrl + 0, 0x21); + write8(misc_mem_clk_cntrl + 1, 0x43); /* GPP CLK5 is only connected to test pads -> disable */ - write8(misc_mem_clk_cntrl + 2, 0x0F); + write8(misc_mem_clk_cntrl + 2, 0x05); /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ write8(misc_mem_clk_cntrl + 3, 0x00); write8(misc_mem_clk_cntrl + 4, 0x00);