Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23710
Change subject: nb/x4x/raminit_ddr2: Refactor clock configuration slightly ......................................................................
nb/x4x/raminit_ddr2: Refactor clock configuration slightly
The result is shorter and (IMHO) more readable code.
Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0 Signed-off-by: Jonathan Neuschäfer j.neuschaefer@gmx.net --- M src/northbridge/intel/x4x/raminit_ddr2.c 1 file changed, 14 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/23710/1
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index e6ba2dc..e28a613 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -722,23 +722,20 @@ }
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { - clkset0(i, &dll_setting_667[CLKSET0]); - clkset1(i, &dll_setting_667[CLKSET1]); - ctrlset0(i, &dll_setting_667[CTRL0]); - ctrlset1(i, &dll_setting_667[CTRL1]); - ctrlset2(i, &dll_setting_667[CTRL2]); - ctrlset3(i, &dll_setting_667[CTRL3]); - cmdset(i, &dll_setting_667[CMD]); - } else { - clkset0(i, &dll_setting_800[CLKSET0]); - clkset1(i, &dll_setting_800[CLKSET1]); - ctrlset0(i, &dll_setting_800[CTRL0]); - ctrlset1(i, &dll_setting_800[CTRL1]); - ctrlset2(i, &dll_setting_800[CTRL2]); - ctrlset3(i, &dll_setting_800[CTRL3]); - cmdset(i, &dll_setting_800[CMD]); - } + struct dll_setting *setting; + + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) + setting = dll_setting_667; + else + setting = dll_setting_800; + + clkset0(i, &setting[CLKSET0]); + clkset1(i, &setting[CLKSET1]); + ctrlset0(i, &setting[CTRL0]); + ctrlset1(i, &setting[CTRL1]); + ctrlset2(i, &setting[CTRL2]); + ctrlset3(i, &setting[CTRL3]); + cmdset(i, &setting[CMD]); }
// XXX if not async mode