[coreboot-gerrit] Change in coreboot[master]: vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW47 FSP Memory map HOB mismatch

[Johnny Lin (Code Review)]

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48228 )

Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW47 FSP Memory map HOB mismatch
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vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW47 FSP Memory map HOB mismatch

Tested=On OCP Delta Lake, verify the memory map hob data are correct.

Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716
Signed-off-by: Johnny Lin 
---
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48228/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
index 53b7305..598d78c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
@@ -159,7 +159,7 @@
   UINT8    NumChPerMC;
   UINT8    numberEntries;                         // Number of Memory Map Elements
   SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
-  UINT8    reserved5[2216];
+  UINT8    reserved5[2249];
   MEMMAP_SOCKET Socket[MAX_SOCKET];
   UINT8    reserved6[1603];