Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger.
BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35666/1
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 5fba04b..76184be 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -214,7 +214,6 @@ /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ @@ -250,6 +249,7 @@ /* EMMC_DATA3 */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* EMMC_DATA4 */ PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, UP_20K, NF1), /* SIO_PWRBTN# */ };
const struct pad_config *variant_gpio_table(size_t *num)