Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74075 )
Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 ......................................................................
mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF), hence update the correct bridge number in the device tree.
TEST: Builds and boots, the device enumerates. [DEBUG] PCI: 00:02.4 [1022/14ee] enabled [DEBUG] PCI: 01:00.0 [144d/a80a] enabled Signed-off-by: Anand Vaikar a.vaikar2021@gmail.com Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74075 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@mailbox.org Reviewed-by: Fred Reitberger reitbergerfred@gmail.com --- M src/mainboard/amd/mayan/devicetree_phoenix.cb 1 file changed, 21 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Fred Reitberger: Looks good to me, approved
diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 9d1a4b3..697db12 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -160,7 +160,7 @@ device ref iommu on end device ref gpp_bridge_2_1 on end # GBE device ref gpp_bridge_2_2 on end # WIFI - device ref gpp_bridge_2_3 on end # NVMe SSD + device ref gpp_bridge_2_4 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)