[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/psp_verstage: Write postcodes after ESPI init

[Avinash Alevoor (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Jon Murphy, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held.
Avinash Alevoor has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62880 )

Change subject: soc/amd/common/psp_verstage: Write postcodes after ESPI init
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Patch Set 1:

(1 comment)

File src/soc/amd/cezanne/Kconfig:

https://review.coreboot.org/c/coreboot/+/62880/comment/68df4d24_2a8ab50e 
PS1, Line 348: PSP_POSTCODES_ON_ESPI
> Mohan/Avinash, […]

Yes, PSP uses ESPI to write postcodes(Prerequisite is the ESPI should be initialized).

In Cezanne, Soft fuse Bit 15 is used to determine if ESPI Init Should be done by PSP or not. (Since we are aligned that ESPI init will be done by verstage, this bit should not be set)