Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Tim Chu.
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80096?usp=email )
Change subject: soc/intel/xeon_sp: Drop unused MACROs ......................................................................
soc/intel/xeon_sp: Drop unused MACROs
Change-Id: I4067a1940f6cb3ee6d40c784877d7906495251a4 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h 3 files changed, 1 insertion(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/80096/1
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 7dbe5ee..e90b3b8 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -14,18 +14,10 @@ #define PAM_LOCK BIT(0) #define SAD_ALL_PAM456_CSR 0x44
-#if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) -#else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) -#endif - #define PCU_IIO_STACK 1 -#define PCU_DEV 30
-#define PCU_CR0_FUN 0 #define PCU_CR0_DEVID 0x344a -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) + #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 #define TURBO_ACTIVATION_RATIO_LOCK BIT(31) @@ -37,9 +29,7 @@ #define PCU_CR0_PMAX 0xf0 #define PMAX_LOCK BIT(31)
-#define PCU_CR1_FUN 1 #define PCU_CR1_DEVID 0x344b -#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c
#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 @@ -65,16 +55,13 @@ #define PCU_CR1_SAPMCTL 0xb0 #define SAPMCTL_LOCK_MASK BIT(31)
-#define PCU_CR2_FUN 2 #define PCU_CR2_DEVID 0x344c -#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) #define DRAM_POWER_INFO_LOCK_UPR BIT(31) #define PCU_CR2_DRAM_PLANE_POWER_LIMIT 0xf0 #define PP_PWR_LIM_LOCK BIT(31)
-#define PCU_CR3_FUN 3 #define PCU_CR3_DEVID 0x344d #define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0x60 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 33b5c42..2fe1b3a 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -27,21 +27,11 @@ #define PAM_LOCK BIT(0) #define SAD_ALL_PAM456_CSR 0x44
-#if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) -#else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) -#endif - #define PCU_IIO_STACK 1 -#define PCU_DEV 30 -#define PCU_CR1_FUN 1 #define PCU_CR1_DEVID 0x2081
-#define PCU_CR0_FUN 0 #define PCU_CR0_DEVID 0x2080
-#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_P_STATE_LIMITS 0xd8 #define P_STATE_LIMITS_LOCK_SHIFT 31 diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 9075728..a1fabb6 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -37,19 +37,11 @@ #define SAD_ALL_PAM0123_CSR 0x80 #define SAD_ALL_PAM456_CSR 0x84
-#if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) -#else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) -#endif - /* PCU [B:31, D:30, F:0->F:6] */ #define PCU_IIO_STACK UNCORE_BUS_1 #define PCU_DEV 30
-#define PCU_CR0_FUN 0 #define PCU_CR0_DEVID 0x3258 -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 #define TURBO_ACTIVATION_RATIO_LOCK BIT(31) @@ -63,9 +55,7 @@ #define PCU_CR0_VR_CURRENT_CONFIG_CFG 0xf8 #define VR_CURRENT_CONFIG_LOCK BIT(31)
-#define PCU_CR1_FUN 1 #define PCU_CR1_DEVID 0x3259 -#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c
#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 @@ -88,9 +78,7 @@ #define PCU_CR1_DESIRED_CORES_CFG2_REG 0xbc #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31)
-#define PCU_CR2_FUN 2 #define PCU_CR2_DEVID 0x325a -#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) #define DRAM_POWER_INFO_LOCK_UPR BIT(31) @@ -99,17 +87,14 @@ #define PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR (PCU_CR2_DRAM_PLANE_POWER_LIMIT_LWR + 4) #define PP_PWR_LIM_LOCK_UPR BIT(31)
-#define PCU_CR3_FUN 3 #define PCU_CR3_DEVID 0x325b #define PCU_CR3_CAPID4 0x94 #define ERR_SPOOFING_DIS 1 -#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0xd8 #define TDP_LOCK BIT(31) #define PCU_CR3_FLEX_RATIO 0xa0 #define OC_LOCK BIT(20)
-#define PCU_CR4_FUN 4 #define PCU_CR4_DEVID 0x325c #define PCU_VIRAL_CONTROL 0x84 #define PCU_FW_ERR_EN (1 << 10) @@ -117,9 +102,7 @@ #define PCU_HW_ERR_EN (1 << 8) #define PCU_EMCA_MODE (1 << 2)
-#define PCU_CR6_FUN 6 #define PCU_CR6_DEVID 0x325e -#define PCU_DEV_CR6(bus) _PCU_DEV(bus, PCU_CR6_FUN) #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR 0xa8 #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR (PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR + 4) #define PLT_PWR_LIM_LOCK_UPR BIT(31)